中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.039 seconds)

    Flexible scheme for adding rules to a NIC pipeline
    11.
    发明授权
    Flexible scheme for adding rules to a NIC pipeline 有权

    公开(公告)号：US12218840B2

    公开(公告)日：2025-02-04

    申请号：US16902371

    申请日：2020-06-16

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Elazar Cohen ,  Shaul Yifrach ,  Parthasarathy Sarangam

    IPC: H04L45/7453 ,  H04L45/00 ,  H04L45/745 ,  H04L69/22

    Abstract: Flexible schemes for adding rules to a NIC pipeline and associated apparatus. Multiple match-action tables are implemented in host memory of a platform defining actions to be taken for matching packet flows. A packet processing pipeline and an exact match (EM) cache is implemented on a network interface, such as a NIC, installed in the platform. A portion of the match-action entries in the host memory match-action tables are cached in the EM cache. Received packets are processed to generate a key that is used as a lookup for the EM cache. If a match is found, the action is taken. For a miss, the key is forwarded to the host software and the match-action tables are searched. For a match, the action is taken, and the entry is added to the EM cache. If no match is found, a new match-action entry is added to a match-action table. Aging-out mechanisms are used for the match-action tables and the EM cache. A multi-hash scheme is used to that supports a very large number of match-action entries.

    Technologies for accelerated HTTP processing with hardware acceleration
    14.
    发明授权
    Technologies for accelerated HTTP processing with hardware acceleration 有权

    公开(公告)号：US11451609B2

    公开(公告)日：2022-09-20

    申请号：US16022949

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

    IPC: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L9/40

    Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

    Technologies for pacing network packet transmissions
    15.
    发明授权
    Technologies for pacing network packet transmissions 有权

    公开(公告)号：US11201829B2

    公开(公告)日：2021-12-14

    申请号：US16415023

    申请日：2019-05-17

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Gregory J. Bowers ,  Ryan E. Hall

    IPC: H04L12/801

    Abstract: Technologies for pacing network packet transmissions include a computing device. The computing device includes a compute engine and a network interface controller (NIC). The NIC is to select a first transmit descriptor from a window of transmit descriptors. The first transmit descriptor is associated with a packet stream. The NIC is also to identify a node of a plurality of nodes of a hierarchical scheduler. The node is associated with the selected first transmit descriptor. The NIC is also to determine whether the identified node has a target amount of transmission credits available and transmit, in response to a determination that the identified node has a target amount of transmission credits available, the network packet associated with the first transmit descriptor to a target computing device.

    TECHNOLOGIES FOR OPTIMIZED QUALITY OF SERVICE ACCELERATION
    16.
    发明申请
    TECHNOLOGIES FOR OPTIMIZED QUALITY OF SERVICE ACCELERATION 审中-公开

    公开(公告)号：US20190044832A1

    公开(公告)日：2019-02-07

    申请号：US16022815

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Duke Hong ,  Yashaswini Raghuram Prathivadi Bhayankaram

    IPC: H04L12/24

    Abstract: Technologies for configuring network quality of service (QoS) parameters include a computing device having a network controller with a scheduler tree. The computing device creates a QoS node for a QoS parameter in a shared layer of a driver QoS tree. The node has status set to exclusive and is associated with a timestamp. If the node is associated with multiple entities, the status may be set to shared. The computing device programs the network controller with a QoS node for the QoS parameter in a shared layer of the scheduler tree. The computing device determines whether available nodes in the shared layer are below a threshold. If so, the computing device finds an oldest exclusive QoS node in the shared layer of the driver QoS tree and moves the node to an exclusive layer of the driver QoS tree and the scheduler tree. Other embodiments are described and claimed.

    TECHNOLOGIES FOR DYNAMICALLY TRANSITIONING NETWORK TRAFFIC HOST BUFFER QUEUES
    17.
    发明申请
    TECHNOLOGIES FOR DYNAMICALLY TRANSITIONING NETWORK TRAFFIC HOST BUFFER QUEUES 审中-公开

    公开(公告)号：US20180091447A1

    公开(公告)日：2018-03-29

    申请号：US15274337

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Matthew A. Jared ,  Duke C. Hong ,  Manasi Deval

    IPC: H04L12/861 ,  H04L12/869 ,  H04L12/801 ,  H04L12/26

    CPC classification number: H04L49/9005 ,  H04L43/08 ,  H04L43/0817 ,  H04L47/11 ,  H04L47/58

    Abstract: Technologies for dynamically transitioning network traffic host buffers of a network computing device include the software abstraction of one or more hardware queues of the network computing device based on a network flow type associated with network traffic received by the network computing device. The network computing device is configured to identify a queue transition event, completing pending transactions in one or more of the software abstracted queues, and transition the abstracted queues to handle the flow type associated with the queue transition event. Additionally, the network computing device is configured to realign the abstracted queues to be associated with one or more hardware components of the network computing device based on the second network traffic flow type, provide a ready indication to a client associated with the abstracted queues that indicates the abstracted queues are ready for polling, and process received network traffic associated with the second network traffic flow type in the abstracted queues. Other embodiments are described herein.

    Concept for segmenting an application buffer into data packets
    20.
    发明授权
    Concept for segmenting an application buffer into data packets 有权

    公开(公告)号：US12010019B2

    公开(公告)日：2024-06-11

    申请号：US17648196

    申请日：2022-01-18

    Applicant: Intel Corporation

    Inventor： Eliel Louzoun ,  Manasi Deval ,  Stephen Doyle ,  Noam Elati ,  Patrick Fleming ,  Gregory Bowers

    IPC: H04L45/74 ,  H04L47/36 ,  H04L49/90

    CPC classification number: H04L45/74 ,  H04L47/365 ,  H04L49/90

    Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.

Patent Agency Ranking