公开(公告)号：US12080781B2

公开(公告)日：2024-09-03

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang ,  Jason Peck ,  Tobias Brown-Heft

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0924

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

公开(公告)号：US11955560B2

公开(公告)日：2024-04-09

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/66 ,  H01L27/22 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20230091603A1

公开(公告)日：2023-03-23

申请号：US17481501

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： Noriyuki Sato ,  Hui Jae Yoo ,  Kevin L. Lin ,  Van H. Le ,  Abhishek Anil Sharma

IPC: H01L35/32 ,  H01L27/16

Abstract: Techniques are provided for forming one or more thermoelectric devices integrated within a substrate of an integrated circuit. Backside substrate processing may be used to form adjacent portions of the substrate that are doped with alternating dopant types (e.g., n-type dopants alternating with p-type dopants). The substrate can then be etched to form pillars of the various n-type and p-type portions. Adjacent pillars of opposite dopant type can be electrically connected together via a conductive layer. Additionally, the top portions of adjacent pillars are connected together, and the bottom portions of a next pair of adjacent pillars being coupled together, in a repeating pattern to ensure that current flows through the length of each of the doped pillars. The flow of current through alternating n-type and p-type doped material creates a heat flux that transfers heat from one end of the integrated thermoelectric device to the other end.

公开(公告)号：US11476408B2

公开(公告)日：2022-10-18

申请号：US16144978

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.

公开(公告)号：US11386951B2

公开(公告)日：2022-07-12

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

公开(公告)号：US20210408291A1

公开(公告)日：2021-12-30

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20200006631A1

公开(公告)日：2020-01-02

申请号：US16024411

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Justin Brockman ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.

公开(公告)号：US20200006626A1

公开(公告)日：2020-01-02

申请号：US16022094

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Ian Young ,  Kaan Oguz ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford ,  Tanay Gosavi

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

公开(公告)号：US20200006424A1

公开(公告)日：2020-01-02

申请号：US16022564

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Atm G. Sarwar ,  Ian Young ,  Hui Jae Yoo ,  Christopher Weigand ,  Benjamin Buford

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01F41/34

Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.

公开(公告)号：US20190386205A1

公开(公告)日：2019-12-19

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  H01F10/32 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.