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    PARALLELIZED AUTHENTICATION ENCODING
    11.
    发明申请
    PARALLELIZED AUTHENTICATION ENCODING 审中-公开

    公开(公告)号：US20170293765A1

    公开(公告)日：2017-10-12

    申请号：US15093200

    申请日：2016-04-07

    Applicant: Intel Corporation

    Inventor： Chang Yong Kang ,  Pierre Laurent

    IPC: G06F21/60 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30101 ,  G06F9/3867 ,  G06F21/64

    Abstract: A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

    Technologies for scalable network packet processing with lock-free rings
    14.
    发明授权
    Technologies for scalable network packet processing with lock-free rings 有权

    公开(公告)号：US10999209B2

    公开(公告)日：2021-05-04

    申请号：US15635581

    申请日：2017-06-28

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris Macnamara ,  Pierre Laurent ,  Sean Harte ,  Peter McCarthy ,  Jacqueline F. Jardim ,  Liang Ma

    IPC: H04L12/873 ,  H04L12/883 ,  H04L12/879 ,  H04L12/927 ,  H04L12/863 ,  H04L12/869

    Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel. Other embodiments are described and claimed.

    Traffic management
    16.
    发明授权
    Traffic management 有权

    公开(公告)号：US10158578B2

    公开(公告)日：2018-12-18

    申请号：US15269295

    申请日：2016-09-19

    Applicant: INTEL CORPORATION

    Inventor： Cristian Florin Dumitrescu ,  Andrey Chilikin ,  Pierre Laurent ,  Kannan Babu Ramia ,  Sravanthi Tangeda

    IPC: H04L12/14 ,  H04L12/869 ,  H04L12/873 ,  H04L12/815 ,  H04L12/863 ,  H04L12/819 ,  H04L12/801 ,  H04L12/813 ,  H04L12/865 ,  H04L12/803 ,  H04L12/851

    Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.

    Packet flow classification
    19.
    发明授权
    Packet flow classification 有权

    公开(公告)号：US09769290B2

    公开(公告)日：2017-09-19

    申请号：US14286975

    申请日：2014-05-23

    Applicant: Intel Corporation

    Inventor： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC: H04L12/743 ,  H04L29/06 ,  H04L12/64

    CPC classification number: H04L69/22 ,  H04L12/6418 ,  H04L45/7453

    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

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