公开(公告)号：US20240222469A1

公开(公告)日：2024-07-04

申请号：US18089966

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66893

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222228A1

公开(公告)日：2024-07-04

申请号：US18089931

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/13 ,  H01L25/0657 ,  H01L27/088 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2924/05032 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113025A1

公开(公告)日：2024-04-04

申请号：US17958283

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/5283 ,  H01L29/0673

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

公开(公告)号：US20240006416A1

公开(公告)日：2024-01-04

申请号：US17855598

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

公开(公告)号：US20240006412A1

公开(公告)日：2024-01-04

申请号：US17855608

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU ,  Cory WEBER ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

公开(公告)号：US20240224508A1

公开(公告)日：2024-07-04

申请号：US18090816

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B12/36 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78696

Abstract: Structures having bit-cost scaling with relaxed transistor area are described. In an example, an integrated circuit structure includes a plurality of plate lines along a first direction. A transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. A plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. The plurality of capacitor structures has a staggered arrangement from a plan view perspective.

公开(公告)号：US20240222438A1

公开(公告)日：2024-07-04

申请号：US18089945

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/26 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/26 ,  H01L29/36 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222435A1

公开(公告)日：2024-07-04

申请号：US18089936

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/105

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/105

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

公开(公告)号：US20240215256A1

公开(公告)日：2024-06-27

申请号：US18088552

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B53/20 ,  H01L23/522 ,  H01L23/528 ,  H10B53/10 ,  H10B61/00

CPC classification number: H10B53/20 ,  H01L23/5226 ,  H01L23/5283 ,  H10B53/10 ,  H10B61/10 ,  H10B61/22

Abstract: Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.

公开(公告)号：US20240215222A1

公开(公告)日：2024-06-27

申请号：US18088543

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Sagar SUTHRAM ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: Structures having backside power delivery and signal routing for front side DRAM are described. In an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the DRAM layer. A backside structure is below and coupled to the transistors of the DRAM layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the DRAM layer.