公开(公告)号：US20190279978A1

公开(公告)日：2019-09-12

申请号：US15754709

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO ,  SEIYON KIM

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In accordance with some embodiments, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in accordance with some embodiments, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.

公开(公告)号：US20190207015A1

公开(公告)日：2019-07-04

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  CORY E. WEBER ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  JIONG ZHANG ,  RITESH JHAVERI ,  SZUYA S. LIAO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

公开(公告)号：US20180248011A1

公开(公告)日：2018-08-30

申请号：US15754887

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/41766 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.