公开(公告)号：US20190102047A1

公开(公告)日：2019-04-04

申请号：US15721768

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Glen J. Anderson ,  Giuseppe Raffa ,  Sangita Sharma ,  Carl S. Marshall ,  Meng Shi ,  Selvakumar Panneer

IPC: G06F3/0481 ,  G06F17/30

Abstract: Systems, apparatuses and methods for technology that provides smart work spaces in ubiquitous computing environments. The technology may determine a task to be performed in a smart work space and perform task modeling, wherein the task modeling includes determining one or more user interfaces involved with the task. One or more placements may be determined for the one or more user interfaces based on one or more ergonomic conditions, an incidence of an interaction, and a length of time of interaction. The technology may position the one or more user interfaces into the smart work space in accordance with the determined one or more placements.

公开(公告)号：US09189945B2

公开(公告)日：2015-11-17

申请号：US14554807

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Carl S. Marshall ,  Selvakumar Panneer

IPC: G08B21/18 ,  G06F1/32

CPC classification number: G08B21/18 ,  G06F1/3212 ,  G06F1/3265 ,  G06F1/3287 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D10/174

Abstract: Systems and methods may provide for identifying an amount of time associated with a user based activity with respect to a battery powered device, and determining a battery drain rate of the battery powered device. An indicator of whether the user based activity can be completed in the amount of time may be generated based on the battery drain rate.

Abstract translation: 系统和方法可以提供用于识别与基于电池供电的设备的基于用户的活动相关联的时间量，以及确定电池供电设备的电池排出速率。 可以基于电池排出速率来生成基于用户的活动是否能够以时间量完成的指示。

公开(公告)号：US12260263B2

公开(公告)日：2025-03-25

申请号：US17528374

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a graphics processing unit (GPU) to: provide a virtual GPU monitor (VGM) to interface over a network with a middleware layer of a client platform, the VGM to interface with the middleware layer using a message passing interface; configure and expose, by the VGM, virtual functions (VFs) of the GPU to the middleware layer of the client platform; intercept, by the VGM, request messages directed to the GPU from the middleware layer, the request messages corresponding to VFs of the GPU to be utilized by the client platform; and generate, by the VGM, a response to the request messages for the middleware client.

公开(公告)号：US20240320184A1

公开(公告)日：2024-09-26

申请号：US18620284

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US12093748B2

公开(公告)日：2024-09-17

申请号：US17133066

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

公开(公告)号：US20240303915A1

公开(公告)日：2024-09-12

申请号：US18610369

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

CPC classification number: G06T15/80 ,  G06N3/08 ,  G06T15/005 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US11893425B2

公开(公告)日：2024-02-06

申请号：US17531005

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to: enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details; load function drivers for the FPGA device in the TEE; create corresponding device files in the TEE based on the FPGA enumeration data; and handle remote MMIO reads and writes to the FPGA device via a network transport protocol.

公开(公告)号：US20230076468A1

公开(公告)日：2023-03-09

申请号：US17468179

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Huimin Chen ,  Selvakumar Panneer ,  Zhengmin Li

IPC: G06F9/445 ,  G06F13/20 ,  G06F9/4401

Abstract: A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

公开(公告)号：US20220100582A1

公开(公告)日：2022-03-31

申请号：US17531005

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06F9/38

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to: enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details; load function drivers for the FPGA device in the TEE; create corresponding device files in the TEE based on the FPGA enumeration data; and handle remote MMIO reads and writes to the FPGA device via a network transport protocol.

公开(公告)号：US20210117246A1

公开(公告)日：2021-04-22

申请号：US17133066

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.