公开(公告)号：US20220179594A1

公开(公告)日：2022-06-09

申请号：US17681512

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Nilesh N. SHAH ,  Chetan CHAUHAN ,  Shigeki TOMISHIMA ,  Nahid HASSAN ,  Andrew Chaang LING

IPC: G06F3/06 ,  G11C13/00 ,  G06N5/04

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US20210391301A1

公开(公告)日：2021-12-16

申请号：US16898198

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Debendra MALLIK ,  Altug KOKER

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package comprises a package substrate and a first die electrically coupled to the package substrate. In an embodiment, an array of die stacks are electrically coupled to the first die. In an embodiment the array of die stacks are between the first die and the package substrate. In an embodiment, individual ones of the die stacks comprise a plurality of second dies arranged in a vertical stack.

公开(公告)号：US20210151437A1

公开(公告)日：2021-05-20

申请号：US17132908

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4763 ,  H01L29/66

Abstract: An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

公开(公告)号：US20200167098A1

公开(公告)日：2020-05-28

申请号：US16779086

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Nilesh N. SHAH ,  Chetan CHAUHAN ,  Shigeki TOMISHIMA ,  Nahid HASSAN ,  Andrew Chaang LING

IPC: G06F3/06 ,  G11C13/00 ,  G06N5/04

Abstract: Examples herein relate to a solid state drive that includes a media, a processing system, and a media command arbiter configured to permit execution of a specific allocation of storage and compute commands based on a configuration, wherein the media command arbiter is to transfer commands to the media based on the configuration. The media can be locally connected to a compute engine processing system that is configurable to perform computations on data stored in the media. The configuration can indicate a number of compute commands and storage commands that are permitted to be performed over a period of time or media bandwidth allocated to compute commands and storage commands. The processing system can include an inference engine that performs one or more of: data pattern recognition, image recognition, augmented reality overlay applications, face recognition, object recognition, or voice recognition, language translation.

公开(公告)号：US20180191512A1

公开(公告)日：2018-07-05

申请号：US15395710

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Shigeki TOMISHIMA

IPC: H04L9/32 ,  G06F21/72

CPC classification number: G06F21/72 ,  G09C1/00 ,  H04L9/0866 ,  H04L2209/12

Abstract: In one embodiment, a physically unclonable function is generated with direct twin cell activation in the absence of execution of a prior write command or refresh operation for the bitcell. For example, a structural bit state activation logic directly activates complementary structural bit states of a pair of twin cells of a bitcell in response to an activation command, without any intervening write bit states generated in the bitcell by write commands or refresh operations preceding the activated structural bit states. Other aspects are described herein.

公开(公告)号：US20160314826A1

公开(公告)日：2016-10-27

申请号：US14696050

申请日：2015-04-24

Applicant: INTEL CORPORATION

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

IPC: G11C11/16

CPC classification number: G11C11/1659 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract translation: 根据本公开的各种实施例，描述了诸如自旋传递转矩（STT）随机存取存储器（RAM），STTRAM的MRAM存储器中的杂散磁场减轻。 在一个实施例中，可以通过产生磁场来补偿可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 在另一个实施例中，可以通过选择性地暂停对一行存储器的访问来临时终止可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 本文描述了其它方面。

公开(公告)号：US20220197806A1

公开(公告)日：2022-06-23

申请号：US17133603

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Satish DAMARAJU ,  Altug KOKER

IPC: G06F12/0844

Abstract: Embodiments disclosed herein include memory architectures with stacked memory dies. In an embodiment, an electronic device comprises a base die and an array of memory dies over and electrically coupled to the base die. In an embodiment, the array of memory dies comprise caches. In an embodiment, a compute die is over and electrically coupled to the array of memory dies. In an embodiment, the compute die comprises a plurality of execution units.

公开(公告)号：US20180218759A1

公开(公告)日：2018-08-02

申请号：US15940811

申请日：2018-03-29

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G11C7/06 ,  G11C11/406 ,  G11C7/10 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C7/06 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4282 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

公开(公告)号：US20180096719A1

公开(公告)日：2018-04-05

申请号：US15282766

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  John B. HALBERT ,  Kuljit S. BAINS

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C5/025 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4091 ,  G11C29/025 ,  G11C29/48

Abstract: Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response to the refresh command, the multiple memory devices initiate refresh with timing offsets relative to another of the memory devices. The timing offsets reduce the instantaneous power surge associated with all memory devices starting refresh simultaneously.

公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.