公开(公告)号：US20250006721A1

公开(公告)日：2025-01-02

申请号：US18215514

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Douglas Stout ,  Tai-Hsuan Wu ,  Xinning Wang ,  Ruth Brain ,  Chin-Hsuan Chen ,  Sivakumar Venkataraman ,  Quan Shi ,  Nikolay Ryzhenko Vladimirovich

IPC: H01L27/02 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

公开(公告)号：US20240332299A1

公开(公告)日：2024-10-03

申请号：US18192601

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Van Le ,  Sudipto Naskar ,  Sukru Yemenicioglu

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.

公开(公告)号：US20240324167A1

公开(公告)日：2024-09-26

申请号：US18189808

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Abhishek Anil Sharma ,  Sukru Yemenicioglu ,  Weimin Han ,  Van Le

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.

公开(公告)号：US11948874B2

公开(公告)日：2024-04-02

申请号：US16914132

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US20240105589A1

公开(公告)日：2024-03-28

申请号：US17936014

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Shao Ming Koh ,  Patrick Morrow ,  June Choi ,  Sukru Yemenicioglu ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

公开(公告)号：US20240429161A1

公开(公告)日：2024-12-26

申请号：US18213963

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Tai-Hsuan Wu ,  Nikolay Ryzhenko Vladimirovich ,  Anand Krishnamoorthy ,  Mikhail Sergeevich Talalay ,  Xinning Wang ,  Quan Shi ,  Ozdemir Akin

IPC: H01L23/528 ,  H01L23/522

Abstract: Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.

公开(公告)号：US12051692B2

公开(公告)日：2024-07-30

申请号：US17176412

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Quan Shi ,  Sukru Yemenicioglu ,  Marni Nabors ,  Nikolay Ryzhenko ,  Xinning Wang ,  Sivakumar Venkataraman

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20240113177A1

公开(公告)日：2024-04-04

申请号：US17957887

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Quan Shi ,  Marni Nabors ,  Charles H. Wallace ,  Xinning Wang ,  Tahir Ghani ,  Andy Chih-Hung Wei ,  Mohit K. Haran ,  Leonard P. Guler ,  Sivakumar Venkataraman ,  Reken Patel ,  Richard Schenker

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

公开(公告)号：US20240113107A1

公开(公告)日：2024-04-04

申请号：US17957821

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Marni Nabors ,  Xinning Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.

公开(公告)号：US11764219B2

公开(公告)日：2023-09-19

申请号：US16700064

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Harshitha Vishwanath ,  Renukprasad Hiremath ,  Sukru Yemenicioglu ,  Ranjith Kumar ,  Ruth Amy Brain

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.