公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC: B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC classification number: B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20230343723A1

公开(公告)日：2023-10-26

申请号：US18216005

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L23/5381 ,  H01L23/3675

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20230015619A1

公开(公告)日：2023-01-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWAIKARTA ,  Robert MAY ,  Sashi KANDANUR ,  Sri Ranga Sai BOYAPATI ,  Srinivas PIETAMBARAM ,  Steve CHO ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Ravindranadh ELURI ,  Hiroki TANAKA ,  Aleksandar ALEKSOV ,  Dilan SENEVIRATNE

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US20210035921A1

公开(公告)日：2021-02-04

申请号：US16526087

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20210035901A1

公开(公告)日：2021-02-04

申请号：US17075533

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.