公开(公告)号：US20190019793A1

公开(公告)日：2019-01-17

申请号：US16080914

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Daniel H, MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.

公开(公告)号：US20170271501A1

公开(公告)日：2017-09-21

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Rafael RIOS ,  Kelin J. KUHN ,  Ian A. YOUNG ,  Justin R. WEBER

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7391

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.

公开(公告)号：US20240395696A1

公开(公告)日：2024-11-28

申请号：US18797197

申请日：2024-08-07

Applicant: Intel Corporation

Inventor： Aaron J. WELSH ,  Christopher M. PELTO ,  David J. TOWNER ,  Mark A. BLOUNT ,  Takayoshi ITO ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Stephanie F. SUNDHOLM ,  Chamara ABEYSEKERA ,  Anil W. DEY ,  Che-Yun LIN ,  Uygar E. AVCI

IPC: H01L23/522

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

公开(公告)号：US20240008290A1

公开(公告)日：2024-01-04

申请号：US17855626

申请日：2022-06-30

Applicant: INTEL CORPORATION

Inventor： Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Kevin P. O'BRIEN ,  Ashish Verma PENUMATCHA ,  Chelsey DOROW ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Sudarat LEE ,  Uygar E. AVCI ,  Sou-Chi CHANG

IPC: H01L27/11507 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48

CPC classification number: H01L27/11507 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/481

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420511A1

公开(公告)日：2023-12-28

申请号：US17850623

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Chia-Ching LIN ,  Carly ROGAN ,  Arnab SEN GUPTA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02645 ,  H01L21/02598 ,  H01L21/02485 ,  H01L29/18

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230116719A1

公开(公告)日：2023-04-13

申请号：US17485305

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11507 ,  H01L27/11514

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices with nitride-based ferroelectric materials. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC: H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220208777A1

公开(公告)日：2022-06-30

申请号：US17134279

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L23/522 ,  H01L27/11507

Abstract: A memory device comprises an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines, wherein the plurality of vias comprises a same metal material as the plate lines.

公开(公告)号：US20220199635A1

公开(公告)日：2022-06-23

申请号：US17129851

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L23/522 ,  H01L27/11507

Abstract: Plate line architectures for 3D-Ferroelectric Random Access Memory (3D-FRAM) are described. In an example, a memory device includes a plurality of bitlines along a first direction and a plurality of wordlines along a second direction orthogonal to the first direction. An access transistor is at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and insulating material are fabricated over the access transistor. Two or more ferroelectric capacitors are over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor.

公开(公告)号：US20220068794A1

公开(公告)日：2022-03-03

申请号：US17129858

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Aaron J. WELSH ,  Christopher M. PELTO ,  David J. TOWNER ,  Mark A. BLOUNT ,  Takayoshi ITO ,  Dragos SEGHETE ,  Christopher R. RYDER ,  Stephanie F. SUNDHOLM ,  Chamara ABEYSEKERA ,  Anil W. DEY ,  Che-Yun LIN ,  Uygar E. AVCI

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.