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    Dynamic power limit sharing in a platform
    12.
    发明授权
    Dynamic power limit sharing in a platform 有权
    动态功率极限共享平台

    公开(公告)号：US09557804B2

    公开(公告)日：2017-01-31

    申请号：US14867490

    申请日：2015-09-28

    Applicant: Intel Corporation

    Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Cesar A. Quiroz ,  Vivek Garg ,  Martin T. Rowland ,  Inder M. Sodhi ,  James S. Burns

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

    Abstract translation: 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，可以实现处理器和存储器模块之间的平台功率预算的动态共享。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。

    Processor having per core and package level P0 determination functionality
    14.
    发明授权
    Processor having per core and package level P0 determination functionality 有权
    具有每个核心和封装级别P0确定功能的处理器

    公开(公告)号：US09141426B2

    公开(公告)日：2015-09-22

    申请号：US13631831

    申请日：2012-09-28

    Applicant: Intel Corporation

    Inventor： Malini K. Bhandaru ,  Matthew M. Bace ,  A Leonard Brown ,  Ian M. Steiner ,  Vivek Garg ,  Eric Dehaemer ,  Scott P. Bobholz

    IPC: G06F9/46 ,  G06F9/48 ,  G06F11/34 ,  G06F1/32

    CPC classification number: G06F9/4881 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F11/3409 ,  G06F2201/865 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

    Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

    Abstract translation: 描述了一种包括处理核心和用于处理核心的多个计数器的处理器。 多个计数器将对由处理核心支持的多个线程中的每个线程计数第一值和第二值。 第一个值反映已经为第一个值对应的线程请求了非睡眠状态的多个周期，以及反映已经请求非睡眠状态和最高性能状态的周期数的第二个值 第二个值的相应线程。 第一个值的相应线程和第二个值的相应线程是相同的线程。

    Managing power consumption in a multi-core processor
    15.
    发明授权
    Managing power consumption in a multi-core processor 有权
    管理多核处理器的功耗

    公开(公告)号：US09075614B2

    公开(公告)日：2015-07-07

    申请号：US13782492

    申请日：2013-03-01

    Applicant: Intel Corporation

    Inventor： Eric Fetzer ,  Reid Riedlinger ,  Don Soltis ,  William Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

    Abstract translation: 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

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