公开(公告)号：US11515407B2

公开(公告)日：2022-11-29

申请号：US16232535

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Paul Fischer ,  Anand Murthy ,  Walid Hafez

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L27/092 ,  H01L21/8252 ,  H01L29/66 ,  H01L21/306 ,  H01L23/00

Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack is located over over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.

公开(公告)号：US20200098746A1

公开(公告)日：2020-03-26

申请号：US16141641

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez ,  Nicholas McKubre

IPC: H01L27/06 ,  H03K3/012 ,  H03J3/20 ,  H03H11/04 ,  H03H11/28 ,  H03H7/01 ,  H03H7/38 ,  H01L29/94

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

公开(公告)号：US20200083360A1

公开(公告)日：2020-03-12

申请号：US16126884

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/31 ,  H01L21/308 ,  H01L27/088

Abstract: III-N transistor structure with modulation in the thickness of a III-N material that induces a 2D carrier gas within another III-N material. A thickness of the III-N material within a first distance between a gate terminal and second transistor terminal may be lower than a thickness of the III-N material within a second distance between the gate terminal and a third transistor terminal. Carrier density within the 2D carrier gas, as driven by the thickness modulation, may be lower within a distance between a gate electrode and a second terminal of the transistor. With lower carrier density, more voltage may be dropped over a given distance. Lateral dimensions of a transistor capable of sustaining a given gate-drain voltage, for example, may be reduced.

公开(公告)号：US10243034B2

公开(公告)日：2019-03-26

申请号：US15667333

申请日：2017-08-02

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid Hafez ,  Chia-Hong Jan

IPC: H01L49/02 ,  H01L27/06 ,  H01L23/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/07

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US12108595B2

公开(公告)日：2024-10-01

申请号：US17001525

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Sumit Ashtekar ,  Rahul Ramaswamy ,  Walid Hafez ,  Hector M. Saavedra Garcia

IPC: H01L21/8238 ,  H01H85/02 ,  H01L29/66 ,  H01L29/78 ,  H10B20/20

CPC classification number: H10B20/20 ,  H01H85/0241 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01H2085/0283

Abstract: A device structure includes a first gate on a first fin, a second gate on a second fin, where the second gate is spaced apart from the first gate by a distance. A fuse spans the distance and is in contact with the first gate and the second gate. A first dielectric is between the first fin and the second fin, where the first dielectric is in contact with, and below, the fuse and a second dielectric is between the first gate and the second gate, where the second dielectric is on the fuse.

公开(公告)号：US20230307449A1

公开(公告)日：2023-09-28

申请号：US17656490

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Aurelia Chi Wang ,  Conor Puls ,  Brian Greene ,  Tofizur Rahman ,  Lin Hu ,  Jaladhi Mehta ,  Chung-Hsun Lin ,  Walid Hafez

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

公开(公告)号：US11562999B2

公开(公告)日：2023-01-24

申请号：US16147733

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Roman Olac-Vaw ,  Nick Lindert ,  Chia-Hong Jan ,  Walid Hafez

IPC: H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78 ,  H01L21/027 ,  H01L29/66 ,  H01L23/522 ,  H01L23/00

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.

公开(公告)号：US11521964B2

公开(公告)日：2022-12-06

申请号：US16024705

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Paul Fischer ,  Walid Hafez ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L27/06 ,  H01L29/872 ,  H01L21/8252 ,  H01L29/205 ,  H01L29/20 ,  H01L27/02 ,  H01L29/778

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20220293738A1

公开(公告)日：2022-09-15

申请号：US17826058

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/20 ,  H01L21/285 ,  H01L29/778 ,  H01L21/033 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L21/321

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

公开(公告)号：US11380679B2

公开(公告)日：2022-07-05

申请号：US16141641

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez ,  Nicholas McKubre

IPC: H01L27/06 ,  H03K3/012 ,  H03J3/20 ,  H01L29/94 ,  H03H11/28 ,  H03H7/01 ,  H03H7/38 ,  H03H11/04

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.