公开(公告)号：US09178010B2

公开(公告)日：2015-11-03

申请号：US13693901

申请日：2012-12-04

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Toshiyuki Hirota ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L21/02 ,  C23C16/455 ,  H01L29/423

CPC classification number: H01L28/60 ,  C23C16/45534 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L29/4234

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract translation: 一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层 电介质掺杂剂材料。 该方法还可用于在体电介质层和第二电极层之间形成阻挡层。 该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

公开(公告)号：US09012298B2

公开(公告)日：2015-04-21

申请号：US13731452

申请日：2012-12-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/02 ,  H01G4/008 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

公开(公告)号：US08847397B2

公开(公告)日：2014-09-30

申请号：US13737263

申请日：2013-01-09

Applicant: Intermolecular, Inc.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52

CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

公开(公告)号：US08815695B2

公开(公告)日：2014-08-26

申请号：US13727898

申请日：2012-12-27

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/92 ,  H01L21/8242 ,  H01L21/316 ,  H01L27/04 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

公开(公告)号：US20140183695A1

公开(公告)日：2014-07-03

申请号：US13731548

申请日：2012-12-31

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

公开(公告)号：US08581319B2

公开(公告)日：2013-11-12

申请号：US13738901

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L29/94

CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

公开(公告)号：US20130119513A1

公开(公告)日：2013-05-16

申请号：US13693901

申请日：2012-12-04

Applicant: Intermolecular, Inc. ,  Elpida Memory , Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Toshiyuki Hirota ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/60 ,  C23C16/45534 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L29/4234

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract translation: 一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层 电介质掺杂剂材料。 该方法还可用于在体电介质层和第二电极层之间形成阻挡层。 该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

公开(公告)号：US09105646B2

公开(公告)日：2015-08-11

申请号：US13731548

申请日：2012-12-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

公开(公告)号：US08878269B2

公开(公告)日：2014-11-04

申请号：US13738831

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Wim Deweerd ,  Sandra G. Malhotra ,  Hiroyuki Ode

IPC: H01L27/108

CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract translation: 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

公开(公告)号：US20140183696A1

公开(公告)日：2014-07-03

申请号：US13737138

申请日：2013-01-09

Applicant: INTERMOLECULAR INC.

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。