公开(公告)号：US20180158931A1

公开(公告)日：2018-06-07

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20230138978A1

公开(公告)日：2023-05-04

申请号：US17453010

申请日：2021-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHANRO PARK ,  Chi-Chun LIU ,  Stuart Sieg ,  Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen

IPC: H01L21/033 ,  H01L21/3213

Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

公开(公告)号：US20230100368A1

公开(公告)日：2023-03-30

申请号：US17483922

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Yann Mignot ,  Su Chen Fan ,  Mary Claire Silvestre ,  Chi-Chun LIU ,  Junli Wang

IPC: H01L23/522 ,  H01L21/768

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

公开(公告)号：US20180308806A1

公开(公告)日：2018-10-25

申请号：US15494671

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Shawn P. FETTEROLF ,  Chi-Chun LIU

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/573 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329

Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.