公开(公告)号：US20220406657A1

公开(公告)日：2022-12-22

申请号：US17351307

申请日：2021-06-18

Applicant: International Business Machines Corporation

Inventor： SOMNATH GHOSH ,  Karen Elizabeth Petrillo ,  Cody J. Murray ,  Ekmini Anuja De Silva ,  Chi-Chun LIU ,  Dominik METZLER ,  John Christopher Arnold

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

公开(公告)号：US20180374935A1

公开(公告)日：2018-12-27

申请号：US16056934

申请日：2018-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20200234957A1

公开(公告)日：2020-07-23

申请号：US16253429

申请日：2019-01-22

Applicant: International Business Machines Corporation

Inventor： Yann MIGNOT ,  Yongan XU ,  Ekmini Anuja DE SILVA ,  Ashim DUTTA ,  Chi-Chun LIU

IPC: H01L21/033

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

公开(公告)号：US20190189775A1

公开(公告)日：2019-06-20

申请号：US16282384

申请日：2019-02-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun LIU ,  Sanjay MEHTA ,  Luciana MELI ,  Muthumanickam SANKARAPANDIAN ,  Kristin SCHMIDT ,  Ankit VORA

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/088

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

公开(公告)号：US20190109212A1

公开(公告)日：2019-04-11

申请号：US15726525

申请日：2017-10-06

Applicant: International Business Machines Corporation

Inventor： Chi-Chun LIU ,  Sanjay MEHTA ,  Luciana MELI ,  Muthumanickam SANKARAPANDIAN ,  Kristin SCHMIDT ,  Ankit VORA

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L27/088

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

公开(公告)号：US20240176584A1

公开(公告)日：2024-05-30

申请号：US18071230

申请日：2022-11-29

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Andrea Fasoli ,  Ankur Agrawal ,  Kyu-hyoun Kim ,  Chi-Chun LIU ,  Mauricio J. Serrano ,  Monodeep Kar ,  Naigang Wang ,  Leland Chang

IPC: G06F7/523

CPC classification number: G06F7/523

Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result.

公开(公告)号：US20230063908A1

公开(公告)日：2023-03-02

申请号：US17461096

申请日：2021-08-30

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Hsueh-Chung Chen ,  Junli Wang ,  Mary Claire Silvestre ,  Chi-Chun LIU

IPC: H01L23/522 ,  H01L49/02

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

公开(公告)号：US20180308807A1

公开(公告)日：2018-10-25

申请号：US15920562

申请日：2018-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Shawn P. FETTEROLF ,  Chi-Chun LIU

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

公开(公告)号：US20240419401A1

公开(公告)日：2024-12-19

申请号：US18335820

申请日：2023-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derrick LIU ,  Ankur AGRAWAL ,  Chi-Chun LIU ,  Shyam RAMJI ,  Naigang WANG

IPC: G06F7/499

Abstract: Various embodiments are provided herein for performing a mathematical calculation in a computing environment. A quantization scheme is implemented, allowing at most one (1) non-zero-valued bit in the mantissa of a floating point number.

公开(公告)号：US20220172776A1

公开(公告)日：2022-06-02

申请号：US17109296

申请日：2020-12-02

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Mary Claire Silvestre ,  Soon-Cheon Seo ,  Chi-Chun LIU ,  FEE LI LIE ,  Chih-Chao Yang ,  Yann Mignot ,  Theodorus E. Standaert

IPC: G11C13/00 ,  G11C11/16 ,  H03K19/20

Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.