公开(公告)号：US20210151556A1

公开(公告)日：2021-05-20

申请号：US17132798

申请日：2020-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Alexander Reznicek ,  Lan Yu

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

公开(公告)号：US20210104627A1

公开(公告)日：2021-04-08

申请号：US16590813

申请日：2019-10-02

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Gen Tsutsui ,  Lan Yu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method for fabricating a vertical transistor device includes forming a plurality of fins on a substrate. The method further includes forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins. The method further includes selectively removing the interlevel dielectric layer between adjacent fins. The method further includes laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity exposing a bottom portion of each fin and extending beyond each fin. The method further includes epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.

公开(公告)号：US20210091230A1

公开(公告)日：2021-03-25

申请号：US16578762

申请日：2019-09-23

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Oleg Gluschenkov ,  Lan Yu ,  Ruilong Xie

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66

Abstract: Embodiments of the present invention are directed to forming a nanosheet field effect transistor (FET) having a low resistivity region that reduces the nanosheet external resistance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. An inner layer is formed over nanosheets in the nanosheet stack. The inner layer includes a first material having a first melting point. An outer layer is formed over the inner layer. The outer layer includes a second material having a second melting point that is lower than the first melting point. A heavily doped region is formed on a surface of the outer layer and the nanosheet stack is annealed at a temperature between the first melting point and the second melting point such that the outer layer is selectively liquified, distributing the dopants throughout the outer layer.

公开(公告)号：US20210020741A1

公开(公告)日：2021-01-21

申请号：US16515526

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Alexander Reznicek ,  Lan Yu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

公开(公告)号：US20200279918A1

公开(公告)日：2020-09-03

申请号：US16290611

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US11942557B2

公开(公告)日：2024-03-26

申请号：US17246762

申请日：2021-05-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lan Yu ,  Andrew M. Greene ,  Wenyu Xu ,  Heng Wu

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor nanosheet device including semiconductor channel layers vertically aligned and stacked one on top of another, separated by a work function metal, and a second layer between two first layers, the second layer and two first layers between the semiconductor channel layers and a substrate. A semiconductor device including a lower first layer, a second layer, and a source drain region between a first set of semiconductor channel layers vertically aligned and stacked one on top of another, and a second set of semiconductor channel layers. A method including forming a stack sacrificial layer, a stack of nanosheet layers, forming a cavity by removing the stack sacrificial layer, and simultaneously forming a first layer on an upper surface of the stack sacrificial layer, on vertical side surfaces of the set of sacrificial gates, and an upper first layer and a lower first layer in a portion of the cavity.

公开(公告)号：US20230299176A1

公开(公告)日：2023-09-21

申请号：US18324240

申请日：2023-05-26

Applicant: International Business Machines Corporation

Inventor： Lan Yu ,  Kangguo Cheng ,  Heng Wu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/42392

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

公开(公告)号：US20230178651A1

公开(公告)日：2023-06-08

申请号：US17545074

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Ruilong Xie ,  Lan Yu ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/66666

Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.

公开(公告)号：US20230178617A1

公开(公告)日：2023-06-08

申请号：US17457448

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Andrew M. Greene ,  Ruilong Xie ,  Lan Yu ,  PIETRO MONTANINI

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41775 ,  H01L21/823807 ,  H01L21/823878

Abstract: Semiconductor channel layers vertically aligned and stacked one on top of another, separated by a gate stack material wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy. Forming a first stack, second stack and third stack of nanosheet layers on a substrate, each including alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another, forming a first sacrificial gate across the first stack, a second sacrificial gate across the second stack and a third sacrificial gate across the third stack, forming an undoped silicon epitaxy between the first and the second stacks and between the second and the third stacks.

公开(公告)号：US11615842B2

公开(公告)日：2023-03-28

申请号：US17121379

申请日：2020-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin W. Brew ,  Wei Wang ,  Injo Ok ,  Lan Yu ,  Youngseok Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C27/00

Abstract: An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.