公开(公告)号：US20160079339A1

公开(公告)日：2016-03-17

申请号：US14484536

申请日：2014-09-12

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Qizhi Liu ,  Zhenzhen Ye ,  Yan Zhang

IPC: H01L49/02 ,  H01L21/762 ,  H01L27/02 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L28/10 ,  H01L21/76283 ,  H01L21/764 ,  H01L23/36 ,  H01L23/645 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00

Abstract: The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.

Abstract translation: 本发明一般涉及半导体结构和制造方法，更具体地说，涉及通过用导热和电绝缘材料填充半导体结构的部分来改善诸如电感器等有源器件的器件的散热，其可以用作 散热到基底。 在一个实施例中，电感器可以形成在其中形成有导热和电绝缘材料的空腔区域之上。 然后，可以通过填充有导热和电绝缘材料的沟槽，将热量从电感器消散到空腔，并且最后到达基底衬底。

公开(公告)号：US20160049501A1

公开(公告)日：2016-02-18

申请号：US14834699

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/732 ,  H01L29/16 ,  H01L29/06 ,  H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

Abstract translation: 各种具体实施例包括集成电路（IC）结构，包括：堆叠区域; 以及位于所述堆叠区域下方并接触的硅衬底，所述硅衬底包括：包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下，所述基极区域包括与所述堆叠区域接触的本征基极，与所述本征基极和所述堆叠区域接触的非本征基极，以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。

公开(公告)号：US09231089B2

公开(公告)日：2016-01-05

申请号：US14694359

申请日：2015-04-23

Applicant: International Business Machines Corporation

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo

IPC: H01L29/737 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/737 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.

公开(公告)号：US20150364611A1

公开(公告)日：2015-12-17

申请号：US14306373

申请日：2014-06-17

Applicant: International Business Machines Corporation

Inventor： Christopher J. Funch ,  Qizhi Liu ,  Dean W. Siegel

IPC: H01L29/868 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L29/868 ,  H01L21/76 ,  H01L21/76264 ,  H01L21/764 ,  H01L28/86 ,  H01L28/90 ,  H01L29/0688 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861

Abstract: Disclosed are semiconductor devices (e.g., diodes, such as PN junction diodes and PIN junction diodes, and capacitors) that have semiconductor bodies with interleaved horizontal portions. In the case of a diode, the semiconductor bodies can have different type conductivities and, optionally, can be separated by an intrinsic semiconductor layer. In the case of a capacitor, the semiconductor bodies can have the same or different type conductivities and can be separated by a dielectric layer. In any case, due to the interleaved horizontal portions, the semiconductor devices each have a relatively large active device region within a relatively small area on an integrated circuit chip. Also disclosed herein are methods of forming such semiconductor devices.

Abstract translation: 公开了具有交错水平部分的半导体本体的半导体器件（例如，二极管，例如PN结二极管和PIN结二极管和电容器）。 在二极管的情况下，半导体主体可以具有不同的类型电导率，并且可选地可以由本征半导体层分离。 在电容器的情况下，半导体主体可以具有相同或不同的类型的电导率，并且可以被介电层分离。 在任何情况下，由于交错的水平部分，半导体器件在集成电路芯片上的相对小的区域内各自具有相对较大的有源器件区域。 本文还公开了形成这种半导体器件的方法。

公开(公告)号：US20150340273A1

公开(公告)日：2015-11-26

申请号：US14283984

申请日：2014-05-21

Applicant: International Business Machines Corporation

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  G02B6/132 ,  G02B6/136 ,  H01L29/06 ,  G02B6/134

CPC classification number: H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

Abstract translation: 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。

公开(公告)号：US20150311283A1

公开(公告)日：2015-10-29

申请号：US14734713

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结型晶体管的器件结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

公开(公告)号：US09159816B2

公开(公告)日：2015-10-13

申请号：US14497579

申请日：2014-09-26

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Qizhi Liu

IPC: H01L29/735 ,  H01L21/8228 ,  H01L29/66 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/737 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

Abstract: Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

Abstract translation: 横向PNP双极结晶体管和横向PNP双极结晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

公开(公告)号：US20150255528A1

公开(公告)日：2015-09-10

申请号：US14196137

申请日：2014-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09087868B2

公开(公告)日：2015-07-21

申请号：US14593282

申请日：2015-01-09

Applicant: International Business Machines Corporation

Inventor： Qizhi Liu

IPC: H01L29/76 ,  H01L29/735 ,  G06F17/50 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/1008 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/73

Abstract: Device structures and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 在基板上形成半导体材料层，在半导体材料层上形成掩模层。 将掩模层图案化以形成到半导体材料层的多个开口。 在掩模层形成和图案化之后，半导体材料层在开口的相应位置被蚀刻以限定第一沟槽，第二沟槽通过半导体材料层的第一部分与第一沟槽分开，该第二部分界定了双极的端子 以及通过半导体材料层的限定隔离基座的第二部分与第一沟槽分离的第三沟槽。 在衬底中的至少部分地使用隔离基座作为位置参考确定的位置处形成沟槽隔离区域。

公开(公告)号：US20150194416A1

公开(公告)日：2015-07-09

申请号：US14147186

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L27/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Abstract translation: 各种实施例包括场效应晶体管（FET）以及形成这种FET的方法。 一种方法包括：在前体结构中形成第一组开口，其具有：具有晶体方向的硅衬底，所述硅衬底基本上与第一氧化物邻接; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物; 以及覆盖所述第二氧化物的牺牲层，其中所述第一组开口各自暴露所述硅衬底; 底切在与硅衬底的晶体方向垂直的方向上蚀刻硅衬底以形成与第一组开口对应的沟槽; 钝化第一组开口中的SiGe层或硅层中的至少一个的暴露表面; 并且用电介质至少部分地填充每个沟槽。