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公开(公告)号：US10755759B2
公开(公告)日：2020-08-25
申请号：US16021575
申请日：2018-06-28
发明人： Martin M. Frank , Jin-Ping Han , Dennis M. Newns , Paul M. Solomon , Xiao Sun
摘要： A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
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公开(公告)号：US10395713B2
公开(公告)日：2019-08-27
申请号：US15859583
申请日：2017-12-31
发明人： Jin Ping Han , Xiao Sun , Teng Yang
IPC分类号： G06N3/06 , G11C11/22 , H03K19/177
摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
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公开(公告)号：US11604647B2
公开(公告)日：2023-03-14
申请号：US16558536
申请日：2019-09-03
发明人： Xiao Sun , Chia-Yu Chen , Naigang Wang , Jungwook Choi , Kailash Gopalakrishnan
摘要： An apparatus includes a memory and a processor coupled to the memory. The processor includes first and second sets of arithmetic units having first and second precision for floating-point computations, the second precision being lower than the first precision. The processor is configured to obtain a machine learning model trained in the first precision, to utilize the second set of arithmetic units to perform inference on input data, to utilize the first set of arithmetic units to generate feedback for updating parameters of the second set of arithmetic units based on the inference performed on the input data by the second set of arithmetic units, to tune parameters of the second set of arithmetic units based at least in part on the feedback generated by the first set of arithmetic units, and to utilize the second set of arithmetic units with the tuned parameters to generate inference results.
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公开(公告)号：US11556763B2
公开(公告)日：2023-01-17
申请号：US16279416
申请日：2019-02-19
发明人： Effendi Leobandung , Malte Rasch , Xiao Sun , Yulong Li , Zhibin Ren
摘要： Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.
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15.发明申请公开(公告)号：US20210064985A1
公开(公告)日：2021-03-04
申请号：US16558585
申请日：2019-09-03
发明人： Xiao Sun , Jungwook Choi , Naigang Wang , Chia-Yu Chen , Kailash Gopalakrishnan
摘要： An apparatus for training and inferencing a neural network includes circuitry that is configured to generate a first weight having a first format including a first number of bits based at least in part on a second weight having a second format including a second number of bits and a residual having a third format including a third number of bits. The second number of bits and the third number of bits are each less than the first number of bits. The circuitry is further configured to update the second weight based at least in part on the first weight and to update the residual based at least in part on the updated second weight and the first weight. The circuitry is further configured to update the first weight based at least in part on the updated second weight and the updated residual.
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公开(公告)号：US10892330B2
公开(公告)日：2021-01-12
申请号：US15202729
申请日：2016-07-06
发明人： Jin P. Han , Xiao Sun
IPC分类号： H01L29/10 , H01L27/092 , G06N3/04 , G06N3/063 , H01L27/24
摘要： A synapse network device includes an array of field effect transistor (FET) devices having controllable channel resistance. Pre-neurons are coupled to the array to provide input pulses to the array on first terminals of the FET devices. Post-neurons are coupled to the array to receive outputs from the array on second terminals of the FET devices and provide feedback to the array on third terminals of the FET devices, wherein a state of the FET devices is indicated based upon signals applied to the FET devices.
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公开(公告)号：US10686039B2
公开(公告)日：2020-06-16
申请号：US16395024
申请日：2019-04-25
发明人： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC分类号： H01L21/28 , H01L29/12 , H01L29/06 , H01L27/085 , H01L23/52 , H01L27/088 , H01L21/8234
摘要： Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
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公开(公告)号：US10658384B2
公开(公告)日：2020-05-19
申请号：US16576441
申请日：2019-09-19
发明人： David J. Frank , Paul M. Solomon , Xiao Sun
IPC分类号： H01L21/02 , H01L27/1159 , H01L29/78 , H01L29/45 , H01L27/092
摘要： A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.
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公开(公告)号：US20190378555A1
公开(公告)日：2019-12-12
申请号：US16550809
申请日：2019-08-26
发明人： Jin Ping Han , Xiao Sun , Teng Yang
IPC分类号： G11C11/22 , H03K19/177
摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
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公开(公告)号：US20190221559A1
公开(公告)日：2019-07-18
申请号：US16360690
申请日：2019-03-21
发明人： Jin-Ping Han , Yulong Li , Dennis M. Newns , Paul M. Solomon , Xiao Sun
IPC分类号： H01L27/06 , H01L27/1159 , H01L21/28 , H01L27/11507
CPC分类号： H01L27/0629 , H01L27/11507 , H01L27/1159 , H01L29/0649 , H01L29/40111 , H01L29/4966 , H01L29/516
摘要： A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
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