公开(公告)号：US20200098863A1

公开(公告)日：2020-03-26

申请号：US16684022

申请日：2019-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Zheng Xu

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

公开(公告)号：US20200082048A1

公开(公告)日：2020-03-12

申请号：US16682365

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US20200082047A1

公开(公告)日：2020-03-12

申请号：US16682304

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US10586875B2

公开(公告)日：2020-03-10

申请号：US16026880

申请日：2018-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zheng Xu ,  Zhenxing Bi ,  Dexin Kong ,  Qianwen Chen

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28

Abstract: A method for fabricating a semiconductor device including a gate-all-around based non-volatile memory device includes forming gate-all-around field effect transistor (GAA FET) channels, depositing tunnel dielectric material around the GAA FET channels to isolate the GAA FET channels, forming a floating gate, including depositing first gate material over the isolated GAA FET channels, and forming at least one control gate, including depositing second gate material over the isolated GAA FET channels.

公开(公告)号：US10585346B2

公开(公告)日：2020-03-10

申请号：US15819213

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F1/38

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

公开(公告)号：US20190332738A1

公开(公告)日：2019-10-31

申请号：US15962461

申请日：2018-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F17/50

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

公开(公告)号：US10394116B2

公开(公告)日：2019-08-27

申请号：US15696505

申请日：2017-09-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

公开(公告)号：US10032858B2

公开(公告)日：2018-07-24

申请号：US15477351

申请日：2017-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Dongbing Shao ,  Zheng Xu

IPC: H01L21/00 ,  H01L49/02

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

公开(公告)号：US10032856B1

公开(公告)日：2018-07-24

申请号：US15414011

申请日：2017-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L21/8242 ,  H01L49/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/283 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact arranged on a basal end of the second electrode.

公开(公告)号：US09991328B2

公开(公告)日：2018-06-05

申请号：US15246912

申请日：2016-08-25

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Wei Wang ,  Zheng Xu

IPC: H01L49/02 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L28/20 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/324

Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.