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    ELECTRONIC ARRAY AND CHIP PACKAGE
    11.
    发明申请
    ELECTRONIC ARRAY AND CHIP PACKAGE 有权
    电子阵列和芯片包装

    公开(公告)号：US20150214297A1

    公开(公告)日：2015-07-30

    申请号：US14166880

    申请日：2014-01-29

    Applicant: Infineon Technologies AG

    Inventor： Volker Strutz ,  Horst Theuss ,  Chee Voon Tan ,  Hui Teng Wang

    IPC: H01L29/06

    CPC classification number: H01L29/0649 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45099

    Abstract: An electronic array may include a first electronic component which has a first operation voltage, a second electronic component which has a second operation voltage, wherein the second operation voltage is different from the first operation voltage and wherein the first electronic component and the second electronic component are arranged over each other, an isolation layer between the first electronic component and the second electronic component, wherein the isolation layer electrically isolates the first electronic component from the second electronic component, at least one connection layer formed at least partially between the isolation layer and the first electronic component or between the isolation layer and the second electronic component, wherein the connection layer includes a first portion and a second portion, wherein the first portion and the second portion each extend from the corresponding electronic component to the isolation layer, wherein the first portion includes an electrically isolating material which fixes the isolation layer to the corresponding electronic component and wherein the second portion includes an electrically conductive material which electrically couples the corresponding electronic component to the isolation layer.

    Abstract translation: 电子阵列可以包括具有第一操作电压的第一电子部件，具有第二操作电压的第二电子部件，其中第二操作电压不同于第一操作电压，并且其中第一电子部件和第二电子部件 在第一电子部件和第二电子部件之间布置有隔离层，其中隔离层将第一电子部件与第二电子部件电隔离，至少一个连接层至少部分地形成在隔离层和 所述第一电子部件或所述隔离层和所述第二电子部件之间，其中所述连接层包括第一部分和第二部分，其中所述第一部分和所述第二部分各自从相应的电子部件延伸到所述隔离层，其中， 第一部分包括a n隔离材料，其将隔离层固定到相应的电子部件，并且其中第二部分包括将相应的电子部件电耦合到隔离层的导电材料。

    Semiconductor package with lead tip inspection feature
    13.
    发明授权
    Semiconductor package with lead tip inspection feature 有权

    公开(公告)号：US11587800B2

    公开(公告)日：2023-02-21

    申请号：US16882008

    申请日：2020-05-22

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Khay Chwan Andrew Saw ,  Chee Voon Tan

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L23/48 ,  H01L23/31

    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device. The sidewall-facing terminal of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

    Semiconductor Package with Lead Tip Inspection Feature
    14.
    发明申请
    Semiconductor Package with Lead Tip Inspection Feature 有权

    公开(公告)号：US20230049564A1

    公开(公告)日：2023-02-16

    申请号：US17973864

    申请日：2022-10-26

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Khay Chwan Andrew Saw ,  Chee Voon Tan

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L23/48 ,  H01L23/31

    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices each of the sidewall-facing terminals is electrically connected to the semiconductor die of the respective packaged semiconductor device. Each of the sidewall-facing terminals of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

    Double-Sided Cooled Molded Semiconductor Package
    18.
    发明申请
    Double-Sided Cooled Molded Semiconductor Package 有权

    公开(公告)号：US20210020550A1

    公开(公告)日：2021-01-21

    申请号：US16924851

    申请日：2020-07-09

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

    Semiconductor device having multiple chips mounted to a carrier
    20.
    发明授权
    Semiconductor device having multiple chips mounted to a carrier 有权
    具有安装到载体上的多个芯片的半导体器件

    公开(公告)号：US09263421B2

    公开(公告)日：2016-02-16

    申请号：US14193897

    申请日：2014-02-28

    Applicant: Infineon Technologies AG

    Inventor： Boon Seong Lee ,  Chee Voon Tan

    IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.

    Abstract translation: 半导体器件包括具有第一表面和与第一表面相对的第二表面的芯片载体。 该装置还包括安装在芯片载体的第一表面上的第一半导体芯片。 第二半导体芯片安装在芯片载体的第二表面上，其中面向芯片载体的第二半导体芯片的第一表面的一部分突出在芯片载体的边缘上。 第一电导体耦合到形成在第二半导体芯片的第一表面的在芯片载体的边缘上突出的部分上的电极。

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