公开(公告)号：US10957686B2

公开(公告)日：2021-03-23

申请号：US16744693

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.

公开(公告)号：US10186508B2

公开(公告)日：2019-01-22

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808 ,  H01L29/40

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20180342447A1

公开(公告)日：2018-11-29

申请号：US15985313

申请日：2018-05-21

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H01L23/495 ,  H02M7/5387 ,  H02M1/084 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  B60Y2200/91 ,  H01L21/4825 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/181 ,  H02M1/084 ,  H02M7/003 ,  H02M7/53871 ,  H01L2924/00012

Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

公开(公告)号：US11598904B2

公开(公告)日：2023-03-07

申请号：US16704873

申请日：2019-12-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Dirk Ahlers ,  Andreas Grassmann ,  Andre Uhlemann

IPC: G02B1/118 ,  H05K3/40 ,  H01L23/31 ,  H01L23/00 ,  H05K1/05 ,  H01L23/28 ,  H05K1/18 ,  H05K1/02 ,  H05K3/00

Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.

公开(公告)号：US10319671B2

公开(公告)日：2019-06-11

申请号：US15985313

申请日：2018-05-21

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H02M7/00 ,  H01L21/48 ,  H01L23/31 ,  H02M1/084 ,  H01L23/495 ,  H02M7/5387

Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

公开(公告)号：US09978672B1

公开(公告)日：2018-05-22

申请号：US15603476

申请日：2017-05-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H01L23/495 ,  H01L21/00 ,  H01L23/52 ,  H02M7/5387 ,  H02M1/084 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  B60Y2200/91 ,  H01L21/4825 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/181 ,  H02M7/003 ,  H01L2924/00012

Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.

公开(公告)号：US09881853B2

公开(公告)日：2018-01-30

申请号：US15089668

申请日：2016-04-04

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Dinkel

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02M7/00 ,  H02M7/44

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49113 ,  H02M7/003 ,  H02M7/44 ,  H02M7/5387

Abstract: A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.

公开(公告)号：US20160072376A1

公开(公告)日：2016-03-10

申请号：US14849655

申请日：2015-09-10

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Frank Auer ,  Herbert Gietler ,  Michael Lenz

IPC: H02M1/08 ,  H02K11/04 ,  H02M7/217 ,  H01L27/07 ,  H01L27/02

CPC classification number: H02M1/08 ,  H01L27/0207 ,  H01L27/0733 ,  H02K11/046 ,  H02M7/217 ,  H02M7/219 ,  H02M2001/0048 ,  H02M2007/2195 ,  Y02B70/1408

Abstract: A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal.

Abstract translation: 整流装置包括布置在单个半导体管芯上的功率晶体管，栅极控制电路和电容器结构。 功率晶体管包括连接到整流装置的第一端子的源极或发射极端子，连接到整流装置的第二端子的漏极或集电极端子以及栅极。 栅极控制电路可操作以基于与第一端子和第二端子之间的电压和电流中的至少一个有关的至少一个参数来控制功率晶体管的栅极处的栅极电压。

公开(公告)号：US11955974B2

公开(公告)日：2024-04-09

申请号：US17810163

申请日：2022-06-30

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Manuel Wilke ,  Benjamin Schmidt ,  Jonas Groenvall

IPC: H03K3/011 ,  H03K17/687

CPC classification number: H03K3/011 ,  H03K17/6871

Abstract: This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.

公开(公告)号：US11862541B2

公开(公告)日：2024-01-02

申请号：US17386793

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Dirk Ahlers ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L23/42 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49555 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49503 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L2924/181

Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.