公开(公告)号：US20180210852A1

公开(公告)日：2018-07-26

申请号：US15924934

申请日：2018-03-19

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US09836318B2

公开(公告)日：2017-12-05

申请号：US14206033

申请日：2014-03-12

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Glenn Farrall ,  Neil Hastie ,  Frank Hellwig ,  Richard Knight ,  Antonio Vilela

IPC: G06F12/00 ,  G06F9/455 ,  G06F9/30 ,  G06F13/28 ,  G06F21/71 ,  G06F21/85 ,  G06F11/00

CPC classification number: G06F9/45558 ,  G06F9/30043 ,  G06F13/28 ,  G06F21/71 ,  G06F21/85 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

公开(公告)号：US12099638B2

公开(公告)日：2024-09-24

申请号：US17403075

申请日：2021-08-16

Applicant: Infineon Technologies AG

Inventor： Avni Bildhaiya ,  Viola Rieger ,  Frank Hellwig ,  Alexander Zeh

IPC: G06F21/74 ,  G06F21/50 ,  G06F21/55 ,  G06F21/62 ,  G07C5/08

CPC classification number: G06F21/74 ,  G06F21/50 ,  G06F21/554 ,  G06F21/62 ,  G07C5/0808

Abstract: A security hardware device is configured to secure a control apparatus. The security hardware device includes a data security domain; a functional safety domain; a data security processor provided in the data security domain and is configured to secure data from unauthorized access or manipulation; a functional safety processor provided in the functional safety domain and is configured to detect functional errors and generate respective safety alerts in response to detecting the functional errors; and a monitoring processor configured to analyze the respective safety alerts provided by the functional safety processor for at least one pattern of safety alerts indicative of a security attack and generate a response signal in response to the respective safety alerts having at least one of the at least one pattern of safety alerts.

公开(公告)号：US12001357B2

公开(公告)日：2024-06-04

申请号：US17686445

申请日：2022-03-04

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Sandeep Vangipuram

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/28 ,  G06F13/30

CPC classification number: G06F13/1689 ,  G06F9/5016 ,  G06F13/1621 ,  G06F13/28 ,  G06F13/30

Abstract: A direct memory access (DMA) circuit is provided. The DMA circuit may include a plurality of groups of direct memory access channels, wherein each of the groups includes at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed, and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups.

公开(公告)号：US11989145B2

公开(公告)日：2024-05-21

申请号：US17671031

申请日：2022-02-14

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Glenn Ashley Farrall ,  Darren Galpin ,  Sandeep Vangipuram

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4031 ,  G06F13/404 ,  G06F13/4045

Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

公开(公告)号：US20230259471A1

公开(公告)日：2023-08-17

申请号：US17671031

申请日：2022-02-14

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Glenn Ashley Farrall ,  Darren Galpin ,  Sandeep Vangipuram

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/404 ,  G06F13/4031 ,  G06F13/4045

Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

公开(公告)号：US10992750B2

公开(公告)日：2021-04-27

申请号：US15872216

申请日：2018-01-16

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Glenn Ashley Farrall ,  Gerhard Wirrer

IPC: H04L29/06 ,  G06F9/48 ,  G06F13/24 ,  G06F9/455 ,  H04L12/931 ,  H04L29/08

Abstract: A service request interrupt router having an interrupt controller mapped to an Interrupt Service Provider (ISP) having virtual ISPs; Service Request Nodes (SRNs) configured to convert respective interrupt signals to corresponding service requests, wherein each of the SRNs is configured to direct its service request to one of the virtual ISPs; and an arbitrator configured to arbitrate among the virtual ISPs in a time-sliced manner, and for each of the virtual ISPs, to arbitrate which of the service requests directed thereto has a highest priority.

公开(公告)号：US10592270B2

公开(公告)日：2020-03-17

申请号：US15784528

申请日：2017-10-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Glenn Farrall ,  Neil Hastie ,  Frank Hellwig ,  Richard Knight ,  Antonio Vilela

IPC: G06F12/00 ,  G06F9/455 ,  G06F21/71 ,  G06F21/85 ,  G06F9/30 ,  G06F13/28 ,  G06F11/00

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

公开(公告)号：US20190222645A1

公开(公告)日：2019-07-18

申请号：US15872216

申请日：2018-01-16

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Glenn Ashley Farrall ,  Gerhard Wirrer

IPC: H04L29/08 ,  G06F9/455 ,  H04L12/931

CPC classification number: H04L67/1097 ,  G06F9/45558 ,  G06F2009/45591 ,  G06F2009/45595 ,  H04L49/356

Abstract: A service request interrupt router having an interrupt controller mapped to an Interrupt Service Provider (ISP) having virtual ISPs; Service Request Nodes (SRNs) configured to convert respective interrupt signals to corresponding service requests, wherein each of the SRNs is configured to direct its service request to one of the virtual ISPs; and an arbitrator configured to arbitrate among the virtual ISPs in a time-sliced manner, and for each of the virtual ISPs, to arbitrate which of the service requests directed thereto has a highest priority.

公开(公告)号：US20170315944A1

公开(公告)日：2017-11-02

申请号：US15140815

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.