公开(公告)号：US20210053148A1

公开(公告)日：2021-02-25

申请号：US16986411

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Ralf Rieske ,  Alexander Binter ,  Wolfgang Diewald ,  Bernhard Goller ,  Heimo Graf ,  Gerald Lackner ,  Jan Richter ,  Roland Rupp ,  Guenter Schagerl ,  Marko Swoboda

IPC: B23K26/0622 ,  H01L21/78 ,  B23K26/00 ,  H01L21/02

Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.

公开(公告)号：US20200273750A1

公开(公告)日：2020-08-27

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US09966293B2

公开(公告)日：2018-05-08

申请号：US14490705

申请日：2014-09-19

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Gerald Lackner ,  Josef Unterweger

IPC: B65D85/02 ,  H01L21/683 ,  H01L21/304

CPC classification number: H01L21/6835 ,  H01L21/304 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably attachable to one another.

公开(公告)号：US11848237B2

公开(公告)日：2023-12-19

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/8234 ,  H01L21/561 ,  H01L21/762 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49562 ,  H01L25/0655 ,  H01L23/3114 ,  H01L23/3135 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US11712749B2

公开(公告)日：2023-08-01

申请号：US16986411

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Ralf Rieske ,  Alexander Binter ,  Wolfgang Diewald ,  Bernhard Goller ,  Heimo Graf ,  Gerald Lackner ,  Jan Richter ,  Roland Rupp ,  Guenter Schagerl ,  Marko Swoboda

IPC: B23K26/0622 ,  H01L21/02 ,  B23K26/00 ,  H01L21/78

CPC classification number: B23K26/0624 ,  B23K26/0006 ,  H01L21/02378 ,  H01L21/7813

Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.

公开(公告)号：US20230098233A1

公开(公告)日：2023-03-30

申请号：US17942441

申请日：2022-09-12

Applicant: Infineon Technologies AG

Inventor： Franz-Josef Pichler ,  Johannes Mueller ,  Christoph Ahamer ,  Gerald Lackner ,  Walter Leitgeb

IPC: H01L21/683

Abstract: A chuck for a laser beam wafer dicing equipment includes a wafer support plate having an upper surface for holding a wafer disposed on a dicing tape. The upper surface includes a topographically structured surface region that partly or completely overlaps an edge of the wafer when the wafer disposed on the dicing tape is placed on the upper surface. The topographically structured surface region provides for a reduction in an area of contact between the upper surface and the dicing tape.

公开(公告)号：US10672664B2

公开(公告)日：2020-06-02

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/8234 ,  H01L21/56 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US12205842B2

公开(公告)日：2025-01-21

申请号：US17942441

申请日：2022-09-12

Applicant: Infineon Technologies AG

Inventor： Franz-Josef Pichler ,  Johannes Mueller ,  Christoph Ahamer ,  Gerald Lackner ,  Walter Leitgeb

IPC: H01T23/00 ,  H01L21/683

Abstract: A chuck for a laser beam wafer dicing equipment includes a wafer support plate having an upper surface for holding a wafer disposed on a dicing tape. The upper surface includes a topographically structured surface region that partly or completely overlaps an edge of the wafer when the wafer disposed on the dicing tape is placed on the upper surface. The topographically structured surface region provides for a reduction in an area of contact between the upper surface and the dicing tape.

公开(公告)号：US20230330769A1

公开(公告)日：2023-10-19

申请号：US18336643

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Ralf Rieske ,  Alexander Binter ,  Wolfgang Diewald ,  Bernhard Goller ,  Heimo Graf ,  Gerald Lackner ,  Jan Richter ,  Roland Rupp ,  Guenter Schagerl ,  Marko David Swoboda

IPC: B23K26/0622 ,  H01L21/02 ,  B23K26/00 ,  H01L21/78

CPC classification number: B23K26/0624 ,  H01L21/02378 ,  B23K26/0006 ,  H01L21/7813

Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.

公开(公告)号：US11302579B2

公开(公告)日：2022-04-12

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.