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    RF RECEIVER WITH TESTING CAPABILITY
    11.
    发明申请
    RF RECEIVER WITH TESTING CAPABILITY 审中-公开

    公开(公告)号：US20160233969A1

    公开(公告)日：2016-08-11

    申请号：US15099130

    申请日：2016-04-14

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Rainer Stuhlberger

    IPC: H04B17/00 ,  H04L7/00 ,  H04B17/14 ,  H04B17/29

    CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

    Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

    Frequency ramp generation in PLL based RF frontend
    12.
    发明授权
    Frequency ramp generation in PLL based RF frontend 有权
    基于PLL的RF前端产生频率斜坡

    公开(公告)号：US09219487B1

    公开(公告)日：2015-12-22

    申请号：US14472431

    申请日：2014-08-29

    Applicant: Infineon Technologies AG

    Inventor： Rainer Stuhlberger ,  Klemens Kordik

    IPC: H03L7/197 ,  H03C3/09 ,  H03L7/085 ,  G01S13/88

    CPC classification number: H03L7/1976 ,  G01S7/35 ,  G01S13/345 ,  G01S13/88 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/085 ,  H03L7/197 ,  H03L7/1974

    Abstract: An RF transceiver circuit is disclosed herein. In accordance with one example of the disclosure the RF transceiver circuit includes a phase-locked-loop (PLL) with a fractional-N multi-modulus divider. The PLL operates in accordance with a PLL clock frequency and generates a frequency modulated RF output signal. The RF transceiver circuit further includes a modulator unit, which is configured to generate a sequence of division values dependent on a set of modulation parameters. The modulator operates in accordance with a system clock frequency, which is lower than the PLL clock frequency. A sample rate conversion unit is coupled between the modulator unit and a fractional-N multi-modulus divider. The sample rate conversion unit is configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency.

    Abstract translation: 本文公开了RF收发器电路。 根据本公开的一个示例，RF收发器电路包括具有分数N个多模式分频器的锁相环（PLL）。 PLL根据PLL时钟频率工作，并产生调频RF输出信号。 RF收发器电路还包括调制器单元，其被配置为生成依赖于一组调制参数的分频值序列。 调制器根据低于PLL时钟频率的系统时钟频率进行工作。 采样率转换单元耦合在调制器单元和分数N多模分频器之间。 采样率转换单元被配置为内插分频比序列，以对应于PLL时钟频率的速率提供分频比的内插序列。

    RF FRONT-END WITH POWER SENSOR CALIBRATION
    16.
    发明申请
    RF FRONT-END WITH POWER SENSOR CALIBRATION 审中-公开
    RF前端带功率传感器校准

    公开(公告)号：US20160329972A1

    公开(公告)日：2016-11-10

    申请号：US15145485

    申请日：2016-05-03

    Applicant: Infineon Technologies AG

    Inventor： Karl DOMINIZI ,  Oliver Frank ,  Herbert Jaeger ,  Herbert Knapp ,  Hao Li ,  Florian Starzer ,  Rainer Stuhlberger ,  Jonas Wursthorn

    IPC: H04B17/00 ,  H04B17/11 ,  H04B17/21

    CPC classification number: H04B17/0085 ,  H04B17/102 ,  H04B17/11 ,  H04B17/18 ,  H04B17/21

    Abstract: One exemplary embodiment of the present invention relates to a circuit that includes at least one RF signal path for an RF signal and at least one power sensor, which is coupled to the RF signal path and configured to generate a sensor signal representing the power of the RF signal during normal operation of the circuit. The circuit further includes a circuit node for receiving an RF test signal during calibration operation of the circuit. The circuit node is coupled to the at least one power sensor, so that the at least one power sensor receives the RF test signal additionally or alternatively to the RF signal and generates the sensor signal as representing the power of the RF test signal.

    Abstract translation: 本发明的一个示例性实施例涉及一种电路，其包括用于RF信号的至少一个RF信号路径和至少一个功率传感器，其耦合到RF信号路径并被配置为产生代表 RF信号在电路正常工作期间。 电路还包括用于在电路的校准操作期间接收RF测试信号的电路节点。 所述电路节点耦合到所述至少一个功率传感器，使得所述至少一个功率传感器另外或替代于所述RF信号接收所述RF测试信号，并且生成所述传感器信号以表示所述RF测试信号的功率。

    RF receiver with testing capability
    17.
    发明授权
    RF receiver with testing capability 有权
    具有测试能力的RF接收机

    公开(公告)号：US09485036B2

    公开(公告)日：2016-11-01

    申请号：US15099130

    申请日：2016-04-14

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Rainer Stuhlberger

    IPC: H04B17/00 ,  H04B17/29 ,  H04L7/00 ,  H04B17/14

    CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

    Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

    Abstract translation: RF接收器件包括芯片封装中的半导体芯片和集成在芯片中的测试信号发生器。 测试信号发生器产生包括第一信息的RF测试信号。 集成在芯片中的RF接收器电路接收RF输入信号，将RF输入信号下变频为中频（IF）或基带，并将下变频信号数字化以获得数字信号。 RF接收信道包括具有第一和第二输入端口和输出端口的耦合器。 输出端口耦合到RF接收器电路的输入端，第一输入端口接收天线信号，第二输入端口从测试信号发生器接收测试信号。 信号处理器集成在芯片中，并且在测试周期期间确定数字信号中的第一信息是否匹配预定标准。

    RF RECEIVER WITH TESTING CAPABILITY
    18.
    发明申请
    RF RECEIVER WITH TESTING CAPABILITY 有权
    具有测试能力的RF接收机

    公开(公告)号：US20160087734A1

    公开(公告)日：2016-03-24

    申请号：US14493610

    申请日：2014-09-23

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Rainer Stuhlberger

    IPC: H04B17/29 ,  H04B17/23

    CPC classification number: H04B17/0085 ,  H04B17/14 ,  H04B17/17 ,  H04B17/23 ,  H04B17/29 ,  H04L7/0054

    Abstract: An RF receiver device includes a semiconductor chip in a chip package, and a test signal generator integrated in the chip. The test signal generator generates an RF test signal including first information. An RF receiver circuit integrated in the chip receives an RF input signal, down-converts the RF input signal into an intermediate frequency (IF) or base band, and digitizes the down-converted signal to obtain a digital signal. An RF receive channel includes a coupler having first and second input ports and an output port. The output port is coupled to the input of the RF receiver circuit, the first input port receives an antenna signal and the second input port receives the test signal from the test signal generator. A signal processor is integrated in the chip and determines, during a test cycle, whether the first information in the digital signal matches a predetermined criterion.

    Abstract translation: RF接收器件包括芯片封装中的半导体芯片和集成在芯片中的测试信号发生器。 测试信号发生器产生包括第一信息的RF测试信号。 集成在芯片中的RF接收器电路接收RF输入信号，将RF输入信号下变频为中频（IF）或基带，并将下变频信号数字化以获得数字信号。 RF接收信道包括具有第一和第二输入端口和输出端口的耦合器。 输出端口耦合到RF接收器电路的输入端，第一输入端口接收天线信号，第二输入端口从测试信号发生器接收测试信号。 信号处理器集成在芯片中，并且在测试周期期间确定数字信号中的第一信息是否匹配预定标准。

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