公开(公告)号：US20190042928A1

公开(公告)日：2019-02-07

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/063 ,  H03M7/30 ,  G11C5/06 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US20240064958A1

公开(公告)日：2024-02-22

申请号：US18386487

申请日：2023-11-02

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Sean T. MA ,  Abhishek SHARMA

IPC: H10B12/00 ,  H01L29/786 ,  H01L23/528 ,  H01L29/417

CPC classification number: H10B12/30 ,  H01L29/78696 ,  H01L23/528 ,  H01L29/78642 ,  H01L29/41733 ,  H01L28/60 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.

公开(公告)号：US20230006067A1

公开(公告)日：2023-01-05

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Van H. LE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US20230005526A1

公开(公告)日：2023-01-05

申请号：US17943044

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: G11C11/406 ,  H01L25/065 ,  H01L25/18

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

公开(公告)号：US20220165735A1

公开(公告)日：2022-05-26

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US20200312973A1

公开(公告)日：2020-10-01

申请号：US16651955

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

公开(公告)号：US20200303381A1

公开(公告)日：2020-09-24

申请号：US16357221

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Elijah KARPOV ,  Brian DOYLE ,  Abhishek SHARMA ,  Prashant MAJHI ,  Pulkit JAIN

IPC: H01L27/11 ,  H01L49/02 ,  H05K1/18

Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

公开(公告)号：US20200227416A1

公开(公告)日：2020-07-16

申请号：US16247321

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Sean T. MA ,  Abhishek SHARMA

IPC: H01L27/108 ,  H01L29/786 ,  H01L23/528 ,  H01L49/02 ,  H01L29/417

Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/45

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20200006427A1

公开(公告)日：2020-01-02

申请号：US16024684

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin O'BRIEN ,  Eungnak HAN ,  Manish CHANDHOK ,  Gurpreet SINGH ,  Nafees KABIR ,  Kevin LIN ,  Rami HOURANI ,  Abhishek SHARMA ,  Hui Jae YOO

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.