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    Bus circuits for memory devices
    14.
    发明授权
    Bus circuits for memory devices 有权
    存储器总线电路

    公开(公告)号：US09343119B2

    公开(公告)日：2016-05-17

    申请号：US14479020

    申请日：2014-09-05

    Applicant: Intel Corporation

    Inventor： Nicolas L. Irizarry ,  Balaji Srinivasan

    IPC: G11C7/22 ,  G11C5/14 ,  G11C13/00 ,  G11C16/30

    CPC classification number: G11C5/147 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C16/30

    Abstract: Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.

    Abstract translation: 总线电路和相关技术的实施例在此公开。 在一些实施例中，总线电路可以包括：源极跟随器布置，包括耦合在电源电压和存储器单元的存取线之间的第一晶体管和第二晶体管，其中第一晶体管和第二晶体管各自具有栅极 并且其中所述访问线是位线或字线; 电容器，其具有耦合到所述第一晶体管的栅极端子并具有耦合到参考电压的第二端子的第一端子; 以及耦合在电容器的第一端子和电压调节器之间的开关。 可以公开和/或要求保护其他实施例。

    Bipolar decoder for crosspoint memory
    15.
    发明授权
    Bipolar decoder for crosspoint memory 有权

    公开(公告)号：US11900998B2

    公开(公告)日：2024-02-13

    申请号：US16948300

    申请日：2020-09-11

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Sandeep Kumar Guliani ,  Mase J. Taub ,  Derchang Kau ,  Ashir G. Shah

    IPC: G11C8/08 ,  G11C13/00

    CPC classification number: G11C13/0028 ,  G11C13/0026

    Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

    Bipolar decoder for crosspoint memory cells
    17.
    发明授权
    Bipolar decoder for crosspoint memory cells 有权

    公开(公告)号：US11114143B2

    公开(公告)日：2021-09-07

    申请号：US16283128

    申请日：2019-02-22

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Sandeep K. Guliani ,  DerChang Kau ,  Ashir G. Shah

    IPC: G11C8/10 ,  G06F3/06

    Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

    Integrated setback read with reduced snapback disturb
    19.
    发明授权
    Integrated setback read with reduced snapback disturb 有权
    集成挫折读取与减少的backback干扰

    公开(公告)号：US09437293B1

    公开(公告)日：2016-09-06

    申请号：US14671471

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

    IPC: G11C7/04 ,  G11C13/00

    CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

    Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例。

    BIPOLAR DECODER FOR CROSSPOINT MEMORY
    20.
    发明申请
    BIPOLAR DECODER FOR CROSSPOINT MEMORY 有权

    公开(公告)号：US20220084589A1

    公开(公告)日：2022-03-17

    申请号：US16948300

    申请日：2020-09-11

    Applicant: Intel Corporation

    Inventor： Balaji Srinivasan ,  Sandeep Kumar Guliani ,  Mase J. Taub ,  DerChang Kau ,  Ashir G. Shah

    IPC: G11C13/00

    Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

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