公开(公告)号：US20190042095A1

公开(公告)日：2019-02-07

申请号：US16111156

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： George VERGIS ,  Bill NALE ,  Derek A. THOMPSON ,  James A. McCALL ,  Rajat AGARWAL ,  Wei P. CHEN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.

公开(公告)号：US20170289850A1

公开(公告)日：2017-10-05

申请号：US15089454

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Bill NALE ,  Pete D VOGT

IPC: H04W28/08 ,  H04W24/02 ,  H04B3/36

CPC classification number: H04W28/085 ,  H04B3/36 ,  H04W24/02

Abstract: A system includes a repeater architecture for commands where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of command signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of command signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share the command bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for commands to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for commands to the first group of memory devices.

公开(公告)号：US20170249266A1

公开(公告)日：2017-08-31

申请号：US15482542

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Bill NALE ,  Raj K. RAMANUJAN ,  Muthukuman P. SWAMINATHAN ,  Tessil THOMAS ,  Taarinya POLEPEDDI

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US20220293162A1

公开(公告)日：2022-09-15

申请号：US17830045

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Bill NALE

IPC: G11C11/406 ,  G06F3/06

Abstract: In a memory subsystem, a controller can randomize the sending of directed refresh management (DRFM) commands for DRFM commands that hit multiple banks at a time. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pseudo target row refresh (pTRR) operations based on addresses associated with activate commands. The controller can randomize the indication of address capture for the memory device. With captured addresses and DRFM commands generated at random, the system can make better use of DRFM commands because the multiple banks are more likely to have addresses for pTRR, and randomization can reduce the ability for a row hammer attack to avoid the DRFM.

公开(公告)号：US20220157374A1

公开(公告)日：2022-05-19

申请号：US17666452

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20210264999A1

公开(公告)日：2021-08-26

申请号：US17315303

申请日：2021-05-08

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Bill NALE ,  Jongwon LEE ,  Sreenivas MANDAVA

IPC: G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00

Abstract: A memory chip is described. The memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation signal is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.

公开(公告)号：US20190354132A1

公开(公告)日：2019-11-21

申请号：US16429872

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： George VERGIS ,  Kuljit S. BAINS ,  Bill NALE

IPC: G06F1/06 ,  G06F13/42

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US20190228813A1

公开(公告)日：2019-07-25

申请号：US16370578

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20190066759A1

公开(公告)日：2019-02-28

申请号：US16178473

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： Bill NALE

IPC: G11C11/4078 ,  G11C11/406 ,  G06F12/02

Abstract: A memory device with internal row hammer mitigation includes randomization for selection of victim rows to refresh for row hammer mitigation. When memory devices connected in groups all use the same probabilistic determination of which row to select for row hammer mitigation, all memory devices could miss refreshing the same victim row, resulting in data loss. With randomization of the selection, the memory devices are more likely to select different potential victim rows for refresh, reducing the risk of data loss. The memory device performs row hammer mitigation during a refresh operation on a row selected based on a recent activate command. Selection of the victim row can be performed with a pseudo-random computation based on a value unique to the memory device in the group.

公开(公告)号：US20190042162A1

公开(公告)日：2019-02-07

申请号：US16104040

申请日：2018-08-16

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Suneeta SAH ,  George VERGIS ,  Dimitrios ZIAKAS ,  Bill NALE ,  Chong J. ZHAO ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.