公开(公告)号：US10998261B2

公开(公告)日：2021-05-04

申请号：US15974493

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Wen Wei Lum ,  Mooi Ling Chang ,  Ping Ping Ooi

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.

公开(公告)号：US10978434B2

公开(公告)日：2021-04-13

申请号：US16774904

申请日：2020-01-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Boon Ping Koh ,  Kooi Chi Ooi

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/00 ,  H01Q21/22 ,  H01Q1/52 ,  H01Q21/00 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L23/538

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

公开(公告)号：US20210098350A1

公开(公告)日：2021-04-01

申请号：US16888155

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Lee Fueng Yap ,  Chan Kim Lee

IPC: H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

公开(公告)号：US20210005547A1

公开(公告)日：2021-01-07

申请号：US16819963

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Mooi Ling Chang ,  Ping Ping Ooi ,  Jackson Chung Peng Kong ,  Wen Wei Lum

IPC: H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/00 ,  H01G4/30 ,  H01L25/065 ,  H01G4/40 ,  H01G4/38

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

公开(公告)号：US20200321674A1

公开(公告)日：2020-10-08

申请号：US16305355

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Hungying Lo ,  Bok Eng Cheah

IPC: H01P3/08 ,  H01L23/498 ,  H05K1/02 ,  H01P3/02

Abstract: One embodiment provides an apparatus. The apparatus includes a first signal trace and a current return path. The current return path includes a plurality of portions. The plurality of portions includes a first portion, a second portion and a third portion. The first portion is included in a first power plane. The second portion is included in a second power plane coplanar with the first power plane and separated from the first power plane by a split. The third portion spans the split and is included in a reference voltage plane. The reference voltage plane is coplanar with the first signal trace. The reference voltage plane is separated from the first power plane and the second power plane by a dielectric material.

公开(公告)号：US10593618B2

公开(公告)日：2020-03-17

申请号：US16017652

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Mooi Ling Chang ,  Ping Ping Ooi ,  Jackson Chung Peng Kong ,  Wen Wei Lum

IPC: H01L23/522 ,  H01L49/02 ,  H01L25/16 ,  H01L23/00 ,  H01G4/30 ,  H01L25/065 ,  H01G4/40 ,  H01G4/38 ,  H01L23/538 ,  H01L23/50

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

公开(公告)号：US10396047B2

公开(公告)日：2019-08-27

申请号：US15977617

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim

IPC: H01L29/00 ,  H01L23/64 ,  H01L23/538 ,  H01L23/552 ,  H01L23/498

Abstract: Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.

公开(公告)号：US10396038B2

公开(公告)日：2019-08-27

申请号：US15505901

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Shanggar Periaman ,  Michael Skinner ,  Yen Hsiang Chew ,  Kheng Tat Mar ,  Ridza Effendi Abd Razak ,  Kooi Chi Ooi

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/495 ,  H01L25/065 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48

Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.

公开(公告)号：US20190206698A1

公开(公告)日：2019-07-04

申请号：US16325665

申请日：2016-09-27

Applicant: Bok Eng CHEAH ,  Min Suet LIM ,  Jackson Chung Peng KONG ,  Howe Yin LOO ,  Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/00 ,  H01L29/06

CPC classification number: H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025

Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.

公开(公告)号：US20190057940A1

公开(公告)日：2019-02-21

申请号：US16079534

申请日：2016-03-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Hungying Louis Lo

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

Abstract: Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may include: an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate, wherein a first thickness of the insulating material between the first step surface and the bottom surface is greater than a second thickness of the insulating material between the second step surface and the bottom surface; a conductive signal pathway extending from the first step surface to the bottom surface; and a conductive shield disposed within the insulating material to shield the conductive signal pathway.