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公开(公告)号：US20200091093A1
公开(公告)日：2020-03-19
申请号：US16450266
申请日：2019-06-24
摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.
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2.发明申请公开(公告)号：US20190181097A1
公开(公告)日：2019-06-13
申请号：US16018984
申请日：2018-06-26
摘要： A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.
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3.发明申请MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME 有权具有中间垂直侧芯片和半导体封装的多模半导体结构公开(公告)号：US20160005718A1
公开(公告)日：2016-01-07
申请号：US14852013
申请日：2015-09-11
IPC分类号： H01L25/065 , H01L23/538 , H01L23/31 , H01L23/48
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译： 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。
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4.发明申请公开(公告)号：US20140091442A1
公开(公告)日：2014-04-03
申请号：US13631392
申请日：2012-09-28
申请人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
发明人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/48 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/32225 , H01L2224/45099 , H01L2924/207
摘要： An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.
摘要翻译： 一种包括具有装置侧的模具的装置; 以及堆积载体，其包括主体，所述主体包括设置在所述管芯的器件侧上的导电材料和介电材料的多个交替层，被构图成多个焊盘或焊盘的极限导电层; 以及栅格阵列，其包括设置在所述主体的所述极限导电层的所述多个焊盘中的相应的一个焊盘上的多个导电柱，所述柱中的至少一个通过至少一个 身体导电材料的一部分。 一种包括形成包括模具的堆积载体的主体的方法，所述积聚载体的主体包括极限导电层，并且在主体的最终导电层上形成包括多个导电柱的栅格阵列。
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5.发明申请公开(公告)号：US20190006333A1
公开(公告)日：2019-01-03
申请号：US16017719
申请日：2018-06-25
摘要： A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.
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6.发明授权公开(公告)号：US09721878B2
公开(公告)日：2017-08-01
申请号：US13631392
申请日：2012-09-28
申请人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
发明人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
IPC分类号： H01L23/48 , H01L23/498 , H01L21/56 , H01L23/538 , H01L25/10 , H01L23/00
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/48 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/32225 , H01L2224/45099 , H01L2924/207
摘要： An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.
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公开(公告)号：US09455218B2
公开(公告)日：2016-09-27
申请号：US13852876
申请日：2013-03-28
申请人： Toong Erh Ooi , Bok Eng Cheah , Nitesh Nimkar
发明人： Toong Erh Ooi , Bok Eng Cheah , Nitesh Nimkar
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L25/10 , H01L25/00 , H01L23/538 , H01L23/50 , H01L21/48 , H01L23/00 , H05K3/46 , H05K1/18
CPC分类号： H01L24/82 , H01L21/4846 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/82005 , H01L2224/82039 , H01L2224/821 , H01L2224/82345 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2225/1076 , H01L2924/12042 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H05K1/185 , H05K3/4682 , H05K2201/10674 , H01L2924/00012 , H01L2924/00
摘要： An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.
摘要翻译： 一种包括模具的设备; 以及堆叠载体，其包括设置在所述管芯的器件侧上的交替的导电材料层和介电材料层，以及包埋所述管芯的厚度尺寸的一部分的电介质材料; 以及多个载体接触点，其设置在所述管芯的器件侧和所述管芯的嵌入的厚度尺寸之间的灰度处，并且被配置为将所述载体连接到衬底。 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在模具的器件侧附近形成堆积载体，其中所述积聚载体包括在所述管芯的器件侧和所述管芯的背面之间限定灰度的介电材料，所述等级包括多个载体接触点 ; 以及将所述管芯和所述载体与所述牺牲衬底分离。
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公开(公告)号：US20160148866A1
公开(公告)日：2016-05-26
申请号：US14555124
申请日：2014-11-26
申请人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
发明人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
IPC分类号： H01L23/528 , H01L21/768 , H01L21/288 , H01L23/00
CPC分类号： H01L21/2885 , H01L21/76802 , H01L21/76879 , H01L23/48 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/13 , H01L2224/1302 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.
摘要翻译： 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。
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9.发明授权High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same 有权用于超薄封装封装结构的高密度封装间连接及其形成工艺公开(公告)号：US08987896B2
公开(公告)日：2015-03-24
申请号：US12890345
申请日：2010-09-24
申请人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
发明人： Bok Eng Cheah , Shanggar Periaman , Kooi Chi Ooi
IPC分类号： H01L23/48 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/10
CPC分类号： H05K1/185 , H01L23/13 , H01L23/49816 , H01L23/49833 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/19106 , H05K1/0298 , H05K1/111 , H05K1/183 , H05K3/10 , H05K3/34 , H05K3/36 , H05K2201/10674 , Y10T29/49126 , Y10T29/4913 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.
摘要翻译： 一种装置包括无芯安装基板和设置在无芯安装基板上的插入件，其具有设置在插入件中的凹部中的芯片和无芯基板。 该装置可以包括与插入器中的互连通道接触的封装间焊料凸块，以及包括顶部封装衬底和设置在顶部封装衬底上的顶部管芯的顶部芯片封装。 顶部封装衬底与封装间焊料凸块接触。
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公开(公告)号：US20140175670A1
公开(公告)日：2014-06-26
申请号：US14190218
申请日：2014-02-26
IPC分类号： H01L25/065 , H01L25/18 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/16 , H01L24/31 , H01L25/18 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/83894 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.
摘要翻译： 描述了电子组件的形成。 一个实施例包括每个包括前侧和后侧的第一和第二半导体管芯结构，前侧包括有源区，背面包括金属区和非金属区。 第一和第二半导体管芯结构包括多个通孔，通孔在有源区和背侧金属区之间形成电连接。 第一和第二半导体管芯结构与第一半导体管芯结构的背侧上的金属区域中的至少一个与第二半导体管芯结构的背面上的金属区域中的至少一个直接接触而堆叠在一起。 描述和要求保护其他实施例。
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