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公开(公告)号：US09870046B2
公开(公告)日：2018-01-16
申请号：US13954979
申请日：2013-07-31
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/24 , G06F9/00 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system
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公开(公告)号：US08683183B2
公开(公告)日：2014-03-25
申请号：US13783963
申请日：2013-03-04
Applicant: Intel Corporation
Inventor： Eric Sprangle
CPC classification number: G06F9/3001 , G06F9/30036 , G06F9/30145 , G06F9/3893
Abstract: In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有多个执行单元的处理器，其中至少一个包括具有包括多个乘法器和加法器的乘法累积（MAC）单元的电路，并且执行用户级乘法 - 累加 指令，用多个元素填充目标存储器，每个元素对应于像素块的像素的绝对值。 描述和要求保护其他实施例。
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公开(公告)号：US11366511B2
公开(公告)日：2022-06-21
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US11054890B2
公开(公告)日：2021-07-06
申请号：US13954980
申请日：2013-07-31
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
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公开(公告)号：US20210089113A1
公开(公告)日：2021-03-25
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
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Patent Agency Ranking
公开(公告)号：US10386915B2
公开(公告)日：2019-08-20
申请号：US15256006
申请日：2016-09-02
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/24 , G06F9/00 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09910483B2
公开(公告)日：2018-03-06
申请号：US14154517
申请日：2014-01-14
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F9/30 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09874926B2
公开(公告)日：2018-01-23
申请号：US14498319
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Douglas Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09495153B2
公开(公告)日：2016-11-15
申请号：US13844111
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Eric Sprangle , Robert D. Cavin , Anwar Rohillah , Douglas M. Carmean
CPC classification number: G06F9/30025 , G06F9/30036 , G06F9/30043
Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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公开(公告)号：US09292900B2
公开(公告)日：2016-03-22
申请号：US14250654
申请日：2014-04-11
Applicant: Intel Corporation
Inventor： Eric Sprangle
CPC classification number: G06T1/20 , G06F3/0644 , G06F9/30043 , G06F9/3867 , G06F9/5016
Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.
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