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公开(公告)号：US11157068B2
公开(公告)日：2021-10-26
申请号：US16258355
申请日：2019-01-25
Applicant: Intel Corporation
Inventor： Dmitriy Berchanskiy , Vinay Raghav , Udaya Natarajan , Huimin Chen
IPC: G06F1/3234 , G06F1/329 , G06F1/26 , G06F1/3228 , G06F1/3287
Abstract: Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.
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公开(公告)号：US10372527B2
公开(公告)日：2019-08-06
申请号：US13942315
申请日：2013-07-15
Applicant: Intel Corporation
Inventor： Huimin Chen , Andrew Martwick , Howard Heck , Robert Dunstan , Dennis Bell , Abdul Hawk Ismail
Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.
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公开(公告)号：US20190044638A1
公开(公告)日：2019-02-07
申请号：US15980442
申请日：2018-05-15
Applicant: Intel Corporation
Inventor： Huimin Chen , David Harriman , Yong Yang
Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.
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公开(公告)号：US20170272231A1
公开(公告)日：2017-09-21
申请号：US15073298
申请日：2016-03-17
Applicant: Intel Corporation
Inventor： Huimin Chen
IPC: H04L7/00
CPC classification number: H04L7/0008 , G06F13/40 , H04L7/0016 , H04L25/14
Abstract: A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.
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公开(公告)号：US09767064B2
公开(公告)日：2017-09-19
申请号：US13729591
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Huimin Chen , Kok Hong Chan
CPC classification number: G06F13/4072 , G06F1/3253 , G06F2213/0042 , Y02D10/151
Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.
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Patent Agency Ranking
公开(公告)号：US20170185547A1
公开(公告)日：2017-06-29
申请号：US14757939
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Steven B. McGowan , Huimin Chen
CPC classification number: G06F13/36 , G06F13/4027 , G06F2213/0042 , H04L25/0298
Abstract: A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.
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17.发明授权公开(公告)号：US09525539B2
公开(公告)日：2016-12-20
申请号：US14919024
申请日：2015-10-21
Applicant: Intel Corporation
Inventor： Huimin Chen , Christopher Hull , Thomas A. Tetzlaff
CPC classification number: H04L5/16 , H04L5/0053 , H04L5/14 , H04W84/12
Abstract: Embodiments of a multi-transceiver wireless communication device and methods for adaptive multi-band communication are generally described herein. In some embodiments, the multi-transceiver wireless communication device is configurable for half-duplex operation and for asymmetrical full-duplex operation on two non-interfering channels. In some embodiments, a contention-based channel access procedure may be performed to attempt to gain access to both a primary channel and an auxiliary channel. A primary transceiver and an auxiliary transceiver may be configured for asymmetrical full-duplex operation when access to both the primary channel and the auxiliary channel is granted. One of the transceivers may be configured for half-duplex operation when access to only one of the channels is granted. During asymmetrical full-duplex operation, the primary transceiver may be configured to communicate data packets using the primary channel, and the auxiliary transceiver may be configured to communicate control packets using an auxiliary channel.
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公开(公告)号：US09252940B2
公开(公告)日：2016-02-02
申请号：US14186683
申请日：2014-02-21
Applicant: Intel Corporation
Inventor： Huimin Chen
CPC classification number: H04L7/0012 , G06F13/38 , H04L7/0008 , H04L7/0054 , H04L7/04 , H04W56/0015 , Y02D10/14 , Y02D10/151
Abstract: Techniques for sampling a data signal are described. An example of an electronic device includes a data bus, a transmitting device coupled to the data bus, and a receiving device coupled to the data bus by a bus interface. The bus interface is to receive a data signal from the transmitting device, wherein the data signal includes a known data pattern. Additionally, the bus interface is to receive a forwarded clock signal from the transmitting device and generate a sampling clock signal based on the forwarded clock signal. Additionally, the bus interface is to sample the known data pattern to obtain phase tracking data and adjust a sampling phase of the sampling clock signal based on the phase tracking data.
Abstract translation: 描述用于采样数据信号的技术。 电子设备的示例包括数据总线，耦合到数据总线的发送设备，以及通过总线接口耦合到数据总线的接收设备。 总线接口用于从发送设备接收数据信号，其中数据信号包括已知的数据模式。 此外，总线接口将从发送设备接收转发的时钟信号，并且基于转发的时钟信号产生采样时钟信号。 此外，总线接口是采样已知的数据模式以获得相位跟踪数据，并且基于相位跟踪数据调整采样时钟信号的采样相位。
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公开(公告)号：US09223385B2
公开(公告)日：2015-12-29
申请号：US13720436
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Huimin Chen , Howard Heck
CPC classification number: G06F1/3253 , G06F13/4004 , G06F13/4086 , Y02B70/126 , Y02D10/151
Abstract: The present disclosure provides techniques for increasing the power efficiency of re-drivers by providing a technique for a re-driver to recognize a variety of power states. A message generator may be located in a host device and may encode a signal indicating a change in a power state. The message may be transmitted to a message decoder located in a re-driver. The message decoder may decode the message and the re-driver may enter a power state in response to the decoded message.
Abstract translation: 本公开提供了通过提供用于重新驱动器来识别各种功率状态的技术来提高重新驱动器的功率效率的技术。 消息发生器可以位于主机设备中，并且可以编码指示功率状态变化的信号。 消息可以被发送到位于重新驱动器中的消息解码器。 消息解码器可以解码消息，并且重新驱动器可以响应于解码的消息而进入功率状态。
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公开(公告)号：US20150242358A1
公开(公告)日：2015-08-27
申请号：US14710002
申请日：2015-05-12
Applicant: Intel Corporation
Inventor： Kok Hong Chan , Huimin Chen
CPC classification number: G06F13/4221 , G06F1/3296 , G06F13/4022 , G06F13/4027 , G06F2213/0042 , G06F2213/4004 , Y02D10/14 , Y02D10/151
Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.
Abstract translation: 这里描述了用于在两个设备之间传送数据的方法和系统。 该方法从中继器中的第一设备检测第一协议的电信号，其中第一协议包括单端信令。 该方法还确定电信号的速度。 此外，该方法基于电信号的速度将第一协议的电信号转换为第二协议的电信号。 第二协议包括差分信令。 此外，该方法将第二协议的电信号发送到第二设备。 此外，当第二协议的电信号指示数据流的结束时，该方法将第二协议的电信号停止到第二设备。
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