公开(公告)号：US11567765B2

公开(公告)日：2023-01-31

申请号：US16487766

申请日：2017-07-01

申请人： Intel Corporation

发明人： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76

摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US10936041B2

公开(公告)日：2021-03-02

申请号：US16369793

申请日：2019-03-29

申请人： Intel Corporation

发明人： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC分类号： G06F1/32 ,  G06F1/324 ,  G06F1/3206

摘要： In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US09753889B2

公开(公告)日：2017-09-05

申请号：US14881111

申请日：2015-10-12

申请人： Intel Corporation

发明人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F12/02 ,  G06F15/80 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US20170192934A1

公开(公告)日：2017-07-06

申请号：US14616323

申请日：2015-02-06

申请人： Intel Corporation

发明人： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC分类号： G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US20150074373A1

公开(公告)日：2015-03-12

申请号：US13977727

申请日：2012-06-02

申请人： INTEL CORPORATION

发明人： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

IPC分类号： G06F15/78 ,  G06F9/30

CPC分类号： G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

摘要翻译： 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。 索引数组保存一组索引和一组对应的掩码元素。 有限状态机有助于散射操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 正在生成的每组地址的缓冲区中分配存储空间。 与生成的地址集相对应的数据元素被复制到缓冲器。 如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。

公开(公告)号：US11681533B2

公开(公告)日：2023-06-20

申请号：US16443593

申请日：2019-06-17

申请人： Intel Corporation

发明人： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F21/57

CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30189 ,  G06F12/1027 ,  G06F21/57 ,  G06F2212/68 ,  G06F2221/034

摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US20200272474A1

公开(公告)日：2020-08-27

申请号：US16443593

申请日：2019-06-17

申请人： Intel Corporation

发明人： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/57

摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US10324857B2

公开(公告)日：2019-06-18

申请号：US15416549

申请日：2017-01-26

申请人： Intel Corporation

发明人： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC分类号： G06F12/10 ,  G06F12/1036 ,  G06F12/1027

摘要： A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US20190171515A1

公开(公告)日：2019-06-06

申请号：US15831195

申请日：2017-12-04

申请人： Intel Corporation

发明人： Zeev Sperber ,  Stanislav Shwartsman ,  Jared W. Stark, IV ,  Lihu Rappoport ,  Igor Yanover ,  George Leifman

IPC分类号： G06F11/07 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F11/0793 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/3802 ,  G06F9/3855 ,  G06F11/0721 ,  G06F12/0215 ,  G06F12/0253 ,  G06F2212/654 ,  G06F2212/702

摘要： A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

公开(公告)号：US10303605B2

公开(公告)日：2019-05-28

申请号：US15214895

申请日：2016-07-20

申请人： INTEL CORPORATION

发明人： Raanan Sade ,  Joseph Nuzman ,  Stanislav Shwartsman ,  Igor Yanover ,  Liron Zur

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F12/0815 ,  G06F12/0893

摘要： An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.