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    ASYMMETRIC SET COMBINED CACHE
    12.
    发明申请
    ASYMMETRIC SET COMBINED CACHE 有权
    不对称设置组合缓存

    公开(公告)号：US20160283392A1

    公开(公告)日：2016-09-29

    申请号：US14671927

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Zvika Greenfield ,  Nadav Bonen ,  Israel Diamand

    IPC: G06F12/08

    CPC classification number: G06F12/0895 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/62

    Abstract: Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may include one or more processing cores for processing of data, and a cache memory to cache data from a main memory for the one or more processing cores, the cache memory including a first cache portion, the first cache portion including a direct-mapped cache, and a second cache portion, the second cache portion including a multi-way cache. The cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion. A coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion.

    Abstract translation: 实施例通常涉及包括直接映射高速缓存部分和多路高速缓存部分的非对称集合组合高速缓存。 处理器可以包括用于处理数据的一个或多个处理核心，以及高速缓存存储器，用于从一个或多个处理核心的主存储器缓存数据，高速缓存存储器包括第一高速缓存部分，第一高速缓存部分包括直接 - 映射的高速缓存和第二高速缓存部分，所述第二高速缓存部分包括多路高速缓存。 高速缓存存储器包括第一高速缓存部分和第二高速缓存部分中的非对称集合，第一高速缓存部分大于第二高速缓存部分。 缓存存储器的协调替换策略提供了第一高速缓存部分和第二高速缓存部分中的数据的替换。

    Memory management to improve power performance
    14.
    发明授权
    Memory management to improve power performance 有权

    公开(公告)号：US11520498B2

    公开(公告)日：2022-12-06

    申请号：US17116991

    申请日：2020-12-09

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Sridhar Muthrasanallur ,  Srinivas Pandruvada ,  Vishwanath Somayaji ,  Prashant Kodali

    IPC: G06F3/06

    Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

    Concurrent accesses of asymmetrical memory sources
    15.
    发明授权
    Concurrent accesses of asymmetrical memory sources 有权

    公开(公告)号：US10558570B2

    公开(公告)日：2020-02-11

    申请号：US15442470

    申请日：2017-02-24

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Zvika Greenfield ,  Randy Osborne

    IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0871 ,  G06F13/16

    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

    Programmable on-die termination timing in a multi-rank system
    16.
    发明授权
    Programmable on-die termination timing in a multi-rank system 有权

    公开(公告)号：US10141935B2

    公开(公告)日：2018-11-27

    申请号：US14865866

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Kuljit S Bains ,  Alexey Kostinsky ,  Nadav Bonen

    IPC: G06F13/00 ,  G11C7/00 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  G06F3/06 ,  G06F13/16

    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

    MEMORY POWER MANAGEMENT METHOD AND APPARATUS
    20.
    发明申请
    MEMORY POWER MANAGEMENT METHOD AND APPARATUS 有权

    公开(公告)号：US20220262427A1

    公开(公告)日：2022-08-18

    申请号：US17178015

    申请日：2021-02-17

    Applicant: Intel Corporation

    Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

    IPC: G11C11/406 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/402

    Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

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