公开(公告)号：US20240021493A1

公开(公告)日：2024-01-18

申请号：US18374587

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/76816 ,  H01L21/565 ,  H01L21/02288 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20210066273A1

公开(公告)日：2021-03-04

申请号：US16557771

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Denis MYASISHCHEV ,  Andrew V. MAZUR ,  Purushotham Kaushik MUTHUR SRINATH ,  Robert M. NICKERSON ,  Shripad GOKHALE

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

公开(公告)号：US20210066167A1

公开(公告)日：2021-03-04

申请号：US16550773

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20150221608A1

公开(公告)日：2015-08-06

申请号：US14686210

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Javier SOTO GONZALEZ ,  Charavana K. GURUMURTHY ,  Robert M. NICKERSON ,  Debendra MALLIK

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/20 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

Abstract translation: 微电子器件包括层叠安装基板，其包括裸片侧和具有设置在安装基板裸片侧的凹部中的表面光洁度层的平台侧。 导电的第一插头与表面光洁度层接触，并且导电的后续插头设置在安装衬底接地侧上，并且其电耦合到导电的第一插头并且直接设置在导电的第一插头的正下方。