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    OPEN-LOOP VOLTAGE REGULATION AND DRIFT COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR (DCO)
    12.
    发明申请
    OPEN-LOOP VOLTAGE REGULATION AND DRIFT COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR (DCO) 审中-公开
    数字控制振荡器（DCO）的开环电压调节和缓冲补偿

    公开(公告)号：US20160365866A1

    公开(公告)日：2016-12-15

    申请号：US15249120

    申请日：2016-08-26

    Applicant: INTEL CORPORATION

    Inventor： Shenggao Li ,  Guluke Tong ,  Sujatha B. Gowder ,  Fulvio Spagna

    IPC: H03L7/099 ,  H03L7/24 ,  H03L5/00

    CPC classification number: H03L7/0991 ,  H03B5/00 ,  H03B5/1246 ,  H03B5/1278 ,  H03K3/0315 ,  H03L1/00 ,  H03L1/02 ,  H03L1/022 ,  H03L5/00 ,  H03L7/07 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18 ,  H03L7/24 ,  H03L2207/06

    Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

    Abstract translation: 实施例包括用于数字控制振荡器（DCO）的开环电压调节和漂移补偿的装置，方法和系统。 在实施例中，通信电路可以包括DCO，开环电压调节器和校准电路。 开环稳压器可以接收校准电压并且可以产生调节电压。 调节电压可以传递到DCO。 在校准模式期间，校准电路可以将调节电压与参考电压进行比较，并根据比较调节校准电压，以将调节电压提供给目标值。 在监视模式期间，校准电路可以接收用于调谐DCO的调谐码，并且基于调谐码的值进一步调整校准电压。

    Low power squelch detector circuit
    13.
    发明授权
    Low power squelch detector circuit 有权
    低功率静噪检测电路

    公开(公告)号：US08843093B2

    公开(公告)日：2014-09-23

    申请号：US13722615

    申请日：2012-12-20

    Applicant: Intel Corporation

    Inventor： Michael V. De Vita ,  Roan M. Nicholson ,  Shenggao Li

    IPC: H04B1/10 ,  H03K5/22 ,  H03K5/24

    CPC classification number: H03K5/2481

    Abstract: Described is an apparatus comprising: a reference generator to provide a first reference and a second reference; a first input coupled to the first reference; a second input coupled to the second reference; and a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal.

    Abstract translation: 描述了一种装置，包括：参考发生器，用于提供第一参考和第二参考; 耦合到第一参考的第一输入; 耦合到第二参考的第二输入; 以及耦合到所述第一和第二输入的比较器，所述比较器接收时钟信号并且根据所述时钟信号的相位来更新输出信号。

    High performance receiver with single calibration voltage
    15.
    发明授权
    High performance receiver with single calibration voltage 有权

    公开(公告)号：US10181969B2

    公开(公告)日：2019-01-15

    申请号：US15372851

    申请日：2016-12-08

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Ji Chen

    IPC: H04L25/03 ,  H04B1/16 ,  H04L1/00 ,  H04L25/02 ,  H04L25/06 ,  H04B1/12

    Abstract: An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

    SUPPLY VOLTAGE ADAPTATION VIA DECISION FEEDBACK EQUALIZER
    16.
    发明申请
    SUPPLY VOLTAGE ADAPTATION VIA DECISION FEEDBACK EQUALIZER 审中-公开

    公开(公告)号：US20180367349A1

    公开(公告)日：2018-12-20

    申请号：US16112391

    申请日：2018-08-24

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Ji Chen

    IPC: H04L25/03 ,  H04L29/06

    Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

    Phase frequency detector
    18.
    发明授权
    Phase frequency detector 有权

    公开(公告)号：US09531393B2

    公开(公告)日：2016-12-27

    申请号：US14624429

    申请日：2015-02-17

    Applicant: Intel Corporation

    Inventor： Wenyan Vivian Jia ,  Shenggao Li ,  Fulvio Spagna

    IPC: H03L7/087 ,  H03D13/00 ,  G04F10/00

    CPC classification number: H03L7/087 ,  G04F10/005 ,  H03D13/00

    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

    COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR APPARATUS AND METHOD
    20.
    发明申请
    COMPENSATION FOR DIGITALLY CONTROLLED OSCILLATOR APPARATUS AND METHOD 审中-公开
    数字控制振荡器装置和方法的补偿

    公开(公告)号：US20150263741A1

    公开(公告)日：2015-09-17

    申请号：US14728877

    申请日：2015-06-02

    Applicant: Intel Corporation

    Inventor： Shenggao Li

    IPC: H03L7/099

    CPC classification number: H03L7/0991 ,  H03B1/00 ,  H03L1/00 ,  H03L7/099 ,  H03L7/104 ,  H03L7/16 ,  H03L2207/06 ,  H03L2207/50

    Abstract: Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to detect a drift in a first control signal and to provide the compensation capacitor array with a second control signal. The second control signal is configured to cause an adjustment of capacitance in the compensation capacitor array based on the detected drift in the first control signal.

    Abstract translation: 可以通过包括补偿电容器阵列和感测逻辑来提供由温度，老化和/或其他效应引起的频率漂移的自动数字感测和补偿。 感测逻辑可以被配置为检测第一控制信号中的漂移并且向补偿电容器阵列提供第二控制信号。 第二控制信号被配置为基于检测到的第一控制信号的漂移来调整补偿电容器阵列中的电容。

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