公开(公告)号：US20230090093A1

公开(公告)日：2023-03-23

申请号：US17479769

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Chelsey DOROW ,  Tanay GOSAVI ,  Chia-Ching LIN ,  Carl NAYLOR ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Urusa ALAAN

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.

公开(公告)号：US20230086499A1

公开(公告)日：2023-03-23

申请号：US17479155

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Uygar E. AVCI ,  Sudarat LEE ,  Carl NAYLOR ,  Tanay GOSAVI

IPC: H01L29/786 ,  H01L29/78

Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

公开(公告)号：US20220149192A1

公开(公告)日：2022-05-12

申请号：US17093452

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Carl NAYLOR ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Shriram SHIVARAMAN ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：US20220140230A1

公开(公告)日：2022-05-05

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20200161535A1

公开(公告)日：2020-05-21

申请号：US16193599

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Dmitri NIKONOV ,  Ian YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

公开(公告)号：US20200083427A1

公开(公告)日：2020-03-12

申请号：US16128426

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20230101604A1

公开(公告)日：2023-03-30

申请号：US17485314

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Tanay GOSAVI ,  Shriram SHIVARAMAN ,  Carl H. NAYLOR ,  Chelsey DOROW ,  Ian A. YOUNG ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/24

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional (3D) memory devices with transition metal dichalcogenide (TMD) channels. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230057992A1

公开(公告)日：2023-02-23

申请号：US17406296

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Raseong KIM ,  Han Wui THEN ,  Ian A. YOUNG

IPC: H01L27/20 ,  H01L29/20 ,  H01L29/778 ,  H03H9/02 ,  H03H9/17 ,  H01L29/66 ,  H03H3/02

Abstract: Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.