公开(公告)号：US20190095361A1

公开(公告)日：2019-03-28

申请号：US15718346

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

IPC: G06F13/16 ,  G06F1/10

CPC classification number: G06F13/1663 ,  G06F1/10 ,  G06F13/1689

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

公开(公告)号：US20180121123A1

公开(公告)日：2018-05-03

申请号：US15721516

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Christopher P. MOZAK ,  Christopher E. COX

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/028

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

公开(公告)号：US20180069692A1

公开(公告)日：2018-03-08

申请号：US15255564

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Ying ZHOU ,  John V. LOVELACE ,  Alberto David PEREZ

IPC: H04L7/033 ,  H04L7/08 ,  H04L7/00

CPC classification number: H04L7/0041 ,  G11C7/00 ,  G11C29/023 ,  G11C29/028 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0331

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

公开(公告)号：US20170031846A1

公开(公告)日：2017-02-02

申请号：US15294671

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/4093 ,  G06F13/40

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。

公开(公告)号：US20150113215A1

公开(公告)日：2015-04-23

申请号：US14580869

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/42 ,  G11C7/10

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。