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公开(公告)号：US20200293456A1
公开(公告)日：2020-09-17
申请号：US16354859
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： MURALI RAMADOSS , VIKRANTH VEMULAPALLI , NIRAN COORAY , WILLIAM B. SADLER , JONATHAN D. PEARCE , MARIAN ALIN PETRE , BEN ASHBAUGH , ELMOUSTAPHA OULD-AHMED-VALL , NICOLAS GALOPPO VON BORRIES , ALTUG KOKER , ARAVINDH ANANTARAMAN , SUBRAMANIAM MAIYURAN , VARGHESE GEORGE , SUNGYE KIM , ANDREI VALENTIN
IPC: G06F12/1009 , G06N20/00
Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20250028675A1
公开(公告)日：2025-01-23
申请号：US18791963
申请日：2024-08-01
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
IPC: G06F15/78 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/80 , G06F17/16 , G06F17/18 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/06 , H03M7/46
Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
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公开(公告)号：US20240053985A1
公开(公告)日：2024-02-15
申请号：US18485089
申请日：2023-10-11
Applicant: Intel Corporation
Inventor： SUBRAMANIAM MAIYURAN , VARGHESE GEORGE , JOYDEEP RAY , ASHUTOSH GARG , JORGE PARRA , SHUBH SHAH , SHUBRA MARWAHA
CPC classification number: G06F9/3001 , G06F9/5011 , G06F17/16 , G06F9/3013 , G06F9/30036
Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.
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公开(公告)号：US20230360307A1
公开(公告)日：2023-11-09
申请号：US18310015
申请日：2023-05-01
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.
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公开(公告)号：US20220122215A1
公开(公告)日：2022-04-21
申请号：US17428216
申请日：2020-03-14
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
IPC: G06T1/60 , G06F12/06 , G06F12/1009 , G06T1/20 , G06F12/0875 , G06F9/38
Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
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Patent Agency Ranking
公开(公告)号：US20220066931A1
公开(公告)日：2022-03-03
申请号：US17310540
申请日：2020-03-14
Applicant: INTEL CORPORATION
Inventor： JOYDEEP RAY , NIRANJAN COORAY , SUBRAMANIAM MAIYURAN , ALTUG KOKER , PRASOONKUMAR SURTI , VARGHESE GEORGE , VALENTIN ANDREI , ABHISHEK APPU , GUADALUPE GARCIA , PATTABHIRAMAN K , SUNGYE KIM , SANJAY KUMAR , PRATIK MAROLIA , ELMOUSTAPHA OULD-AHMED-VALL , VASANTH RANGANATHAN , WILLIAM SADLER , LAKSHMINARAYANAN STRIRAMASSARMA
IPC: G06F12/0802
Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.
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公开(公告)号：US20200293488A1
公开(公告)日：2020-09-17
申请号：US16354782
申请日：2019-03-15
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , ARAVINDH ANANTARAMAN , ABHISHEK R. APPU , ALTUG KOKER , ELMOUSTAPHA OULD-AHMED-VALL , VALENTIN ANDREI , SUBRAMANIAM MAIYURAN , NICOLAS GALAPPO VON BORRIES , VARGHESE GEORGE , MIKE MACPHERSON , BEN ASHBAUGH , MURALI RAMADOSS , VIKRANTH VEMULAPALLI , WILLIAM SADLER , JONATHAN PEARCE , SUNGYE KIM
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20220156343A1
公开(公告)日：2022-05-19
申请号：US17527882
申请日：2021-11-16
Applicant: Intel Corporation
Inventor： SUBRAMANIAM MAIYURAN , JORGE PARRA , SUPRATIM PAL , ASHUTOSH GARG , SHUBRA MARWAHA , CHANDRA GURRAM , DARIN STARKEY , DURGESH BORKAR , VARGHESE GEORGE
Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.
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公开(公告)号：US20210349848A1
公开(公告)日：2021-11-11
申请号：US17321885
申请日：2021-05-17
Applicant: Intel Corporation
Inventor： JOYDEEP RAY , ARAVINDH ANANTARAMAN , ABHISHEK R. APPU , ALTUG KOKER , ELMOUSTAPHA OULD-AHMED-VALL , VALENTIN ANDREI , SUBRAMANIAM MAIYURAN , NICOLAS GALOPPO VON BORRIES , VARGHESE GEORGE , MIKE MACPHERSON , BEN ASHBAUGH , MURALI RAMADOSS , VIKRANTH VEMULAPALLI , WILLIAM SADLER , JONATHAN PEARCE , SUNGYE KIM
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20200051309A1
公开(公告)日：2020-02-13
申请号：US16537140
申请日：2019-08-09
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
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