中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.016 seconds)

    A-priori-probability-phase-estimation for digital phase-locked loops
    11.
    发明授权
    A-priori-probability-phase-estimation for digital phase-locked loops 有权
    数字锁相环的先验概率相位估计

    公开(公告)号：US09231602B1

    公开(公告)日：2016-01-05

    申请号：US14490115

    申请日：2014-09-18

    Applicant: Intel IP Corporation

    Inventor： Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Ran Shimon ,  Ashoke Ravi

    IPC: H03L7/06 ,  H03L7/08 ,  G04F10/00

    CPC classification number: G04F10/005 ,  H03L7/085 ,  H03L2207/50

    Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

    Abstract translation: 数字锁相环用时间数字转换器和估计与时间数字转换器的量化输出相关联的未量化相位的先验概率相位估计分量或估计器分量进行操作。 时间 - 数字转换器产生量化值作为本地振荡器的本地振荡器信号和参考时钟的参考信号的量化输出。 估计分量从作为与时间 - 数字转换器相关的先验数据和量化值的边界的函数的量化值估计相位值。

    DPLL with adjustable delay in integer operation mode
    13.
    发明授权
    DPLL with adjustable delay in integer operation mode 有权

    公开(公告)号：US10686451B2

    公开(公告)日：2020-06-16

    申请号：US16465515

    申请日：2016-12-30

    Applicant: Intel IP Corporation

    Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Nati Dinur ,  Gil Horovitz ,  Rotem Banin

    IPC: H03L7/081 ,  H04L7/033 ,  H03L7/099 ,  H03L7/093

    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

    PHASE SYNCHRONIZATION BETWEEN TWO PHASE LOCKED LOOPS
    14.
    发明申请
    PHASE SYNCHRONIZATION BETWEEN TWO PHASE LOCKED LOOPS 审中-公开

    公开(公告)号：US20180375519A1

    公开(公告)日：2018-12-27

    申请号：US15634183

    申请日：2017-06-27

    Applicant: Intel IP Corporation

    Inventor： Michael Kerner ,  Elan Banin ,  Yair Dgani ,  Evgeny Shumaker ,  Danniel Nahmanny ,  Gil Horovitz

    IPC: H03L7/087

    Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

    Deterministic jitter removal using a closed loop digital-analog mechanism
    19.
    发明授权
    Deterministic jitter removal using a closed loop digital-analog mechanism 有权

    公开(公告)号：US09923563B1

    公开(公告)日：2018-03-20

    申请号：US15389520

    申请日：2016-12-23

    Applicant: Intel IP Corporation

    Inventor： Gil Horovitz ,  Elan Banin ,  Igal Kushnir ,  Aryeh Farber ,  Ran Krichman ,  Ofir Degani ,  Rotem Banin

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03K5/1565 ,  H03L7/0805 ,  H03L7/085 ,  H03L2207/10

    Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

Patent Agency Ranking