公开(公告)号：US09933844B2

公开(公告)日：2018-04-03

申请号：US14953705

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/329 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments relate to clustering execution in a processing system. An aspect includes accessing a control flow graph that defines a data dependency and an execution sequence of a plurality of tasks of an application that executes on a plurality of system components. The execution sequence of the tasks in the control flow graph is modified as a clustered control flow graph that clusters active and idle phases of a system component while maintaining the data dependency. The clustered control flow graph is sent to an operating system, where the operating system utilizes the clustered control flow graph for scheduling the tasks.

公开(公告)号：US20160378550A1

公开(公告)日：2016-12-29

申请号：US14950934

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Ramon Bertran Monfort ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Hans M. Jacobson ,  William J. Song ,  Karthik V. Swaminathan ,  Augusto J. Vega ,  Liang Wang

IPC: G06F9/48 ,  G06F9/54

CPC classification number: G06F8/443 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/4843 ,  G06F9/4887 ,  G06F9/4893 ,  G06F9/543 ,  Y02D10/24

Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

Abstract translation: 一个方面包括优化应用程序工作流程。 优化包括通过确定与嵌入式系统处理器的操作控制旋钮相关的至少一个基准度量来表征应用程序工作流程。 应用程序工作流执行由服务器系统支持的无线连接的系统集群的至少一个移动嵌入式系统遇到的实时计算任务。 应用程序工作流的优化还包括对满足至少一个运行时约束的应用工作流的至少一个基准度量执行优化操作。 输出作为执行优化操作的结果的注释工作流。

公开(公告)号：US20160364364A1

公开(公告)日：2016-12-15

申请号：US14948656

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F15/173 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F13/362 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/17337

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

公开(公告)号：US20160364352A1

公开(公告)日：2016-12-15

申请号：US14739014

申请日：2015-06-15

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/17337

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

Abstract translation: 提供处理元件之间数据的直接通信。 一个方面包括由第一处理单元通过一个处理间链接总线发送数据。 数据经由数据交换部件发往另一个处理元件，该数据交换部件经由设置在第一处理元件和第二处理元件的相应复用器之间的通信线路耦合在第一处理元件和第二处理元件之间。 另一方面包括由数据交换组件确定数据是否已经在数据交换元件处被接收。 如果是这样，则在数据交换组件的寄存器中设置指示符，并将数据转发到另一处理单元。 设置指示灯使第一个处理元件停止。 如果没有接收到数据，则在数据交换组件等待接收数据的同时处理元件停止。

公开(公告)号：US20160363916A1

公开(公告)日：2016-12-15

申请号：US14736758

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Bryan S. Rosenburg

IPC: G05B15/02

CPC classification number: G05B15/02

Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.

Abstract translation: 计算机检测进程访问影子控制页面的请求，其中阴影控制页面允许对一个或多个设备的进程访问。 计算机将阴影控制页面和一个密钥分配给与请求相关联的进程。 计算机通过所分配的影子控制页面检测该过程的请求，以从一个或多个设备创建设备子集。 计算机将详细描述设备子集与所分配的密钥之间的关联的信息输入到子集定义表中，其中子集定义表包括一个或多个密钥和一个或多个相应的子集。

公开(公告)号：US20160313947A1

公开(公告)日：2016-10-27

申请号：US15198868

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract translation: 根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。 存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控​​制器。 存储器访问请求在存储器控制器处被接收。 将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。 存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

公开(公告)号：US20160239066A1

公开(公告)日：2016-08-18

申请号：US15137197

申请日：2016-04-25

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.

公开(公告)号：US20150286261A1

公开(公告)日：2015-10-08

申请号：US14245301

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.

Abstract translation: 实施例涉及将数据存储在存储器中。 一个方面包括将功率节省技术应用于处理器的至少一个子集。 计划由处理器执行的待处理工作项目被监视。 基于省电技术对待处理的工作项进行分组。 该分组包括延迟至少一个未决工作项目的预定执行时间，以增加将功率节省技术应用于处理器的时钟周期的总数。 确定已经满足执行标准。 待处理的工作项目将根据满足的执行标准和分组执行。

公开(公告)号：US09110734B2

公开(公告)日：2015-08-18

申请号：US13674224

申请日：2012-11-12

Applicant: International Business Machines Corporation

Inventor： Hans M. Jacobson ,  Ravi Nair ,  John K. P. O'Brien ,  Zehra N. Sura

IPC: G06F9/50 ,  G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/45

CPC classification number: G06F9/5094 ,  G06F1/329 ,  G06F8/41 ,  G06F9/46 ,  G06F9/4893 ,  Y02D10/24

Abstract: A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement.

Abstract translation: 异构处理系统包括用于在异构处理系统中执行功率约束代码生成和调度工作的编译器。 编译器生成可由计算机执行的源代码。 编译器执行一个方法。 该方法包括将异构处理系统的功率预算分成离散数量的功率令牌。 每个功率令牌具有相等的功率单位。 该方法还包括确定在异构处理系统的处理元件上执行代码段的功率需求。 该确定基于处理元件和代码段的特性。 该方法还包括在运行时向处理元件分配至少一个功率令牌以满足功率需求。

公开(公告)号：US20140229776A1

公开(公告)日：2014-08-14

申请号：US13765320

申请日：2013-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alan Gara ,  Hans M. Jacobson

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G01R31/30 ,  G01R31/3171 ,  G01R31/318525 ,  G11C29/06 ,  G11C2029/0409

Abstract: An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.

Abstract translation: 用于检测电路中硬错误的装置包括存储装置和处理电路。 存储器中存储有测试数据和正常数据。 处理电路包括与至少一组输入锁存器和至少一组输出锁存器串联的组合逻辑。 该装置包括测试控制模块，该测试控制模块被配置为控制处理电路，以阻止通过处理电路的正常数据流，并且通过处理电路运行测试数据，同时使处理电路处于应力状态。