-
11.发明授权Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction 有权基于纳米线磁隧道结中的电流诱导畴壁运动的多位非易失性存储器公开(公告)号：US08923039B2
公开(公告)日：2014-12-30
申请号：US13670064
申请日：2012-11-06
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , B82Y99/00 , G11C7/1006 , G11C11/161 , G11C11/5607 , G11C19/0808 , G11C19/0841 , Y10S977/762
摘要： A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, the selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
摘要翻译： 提供了一种用于在畴壁纳米线磁性结装置中存储多个位的机制。 基于使用单畴壁的畴壁纳米线磁性结装置的电阻对多个位进行编码。 移动单畴壁以改变畴壁纳米线磁结装置的电阻以编码所选择的位。 检查电阻以确保其对应于所选位的预选电阻。 响应于对应于所选位的预选电阻的电阻，存储所选择的位。 响应于不是所选位的预选电阻的电阻，单畴壁移动直到电阻对应于预选电阻。
-
公开(公告)号：US20140356979A1
公开(公告)日：2014-12-04
申请号：US13971518
申请日：2013-08-20
IPC分类号： H01L43/12
摘要： A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.
-
公开(公告)号：US09553128B1
公开(公告)日：2017-01-24
申请号：US14755188
申请日：2015-06-30
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1659 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
-
14.发明授权Method and apparatus for controlled application of Oersted field to magnetic memory structure 有权将奥斯特德磁场控制应用于磁存储器结构的方法和装置公开(公告)号：US08767432B1
公开(公告)日：2014-07-01
申请号：US13710616
申请日：2012-12-11
CPC分类号： G11C19/0841 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C19/08
摘要： An apparatus for applying Oersted fields to a magnetic memory device comprises a first metal layer; a first insulating layer positioned on the first metal layer; a magnetic shift register wire positioned on the first insulating layer; a second insulating layer positioned on the magnetic shift register wire; a second metal layer positioned on the second insulating layer; a first conducting wire positioned in the first metal layer and extending transverse to the magnetic shift register wire; and a second conducting wire positioned in the second metal layer and extending transverse to the magnetic shift register wire. The first conducting wire is offset relative to the second conducting wire, the offset being defined by a distance between a first axis normal to the magnetic shift register wire and through the first conducting wire and a second axis normal to the magnetic shift register wire and through the second conducting wire.
摘要翻译： 一种将奥斯特德场施加到磁存储器件的装置包括第一金属层; 定位在第一金属层上的第一绝缘层; 位于所述第一绝缘层上的磁性移位寄存器线; 定位在磁移位寄存器线上的第二绝缘层; 位于所述第二绝缘层上的第二金属层; 位于所述第一金属层中并横向于所述磁性移位寄存器线延伸的第一导线; 以及位于第二金属层中并横向于磁性移位寄存器线延伸的第二导线。 第一导线相对于第二导线偏移，偏移由通常与磁移位寄存器导线垂直的第一轴与第一导线之间的距离和与磁移位寄存器线垂直的第二轴定义， 第二根导线。
-
15.发明申请公开(公告)号：US20140160829A1
公开(公告)日：2014-06-12
申请号：US13710616
申请日：2012-12-11
IPC分类号： G11C19/08
CPC分类号： G11C19/0841 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C19/08
摘要： An apparatus for applying Oersted fields to a magnetic memory device comprises a first metal layer; a first insulating layer positioned on the first metal layer; a magnetic shift register wire positioned on the first insulating layer; a second insulating layer positioned on the magnetic shift register wire; a second metal layer positioned on the second insulating layer; a first conducting wire positioned in the first metal layer and extending transverse to the magnetic shift register wire; and a second conducting wire positioned in the second metal layer and extending transverse to the magnetic shift register wire. The first conducting wire is offset relative to the second conducting wire, the offset being defined by a distance between a first axis normal to the magnetic shift register wire and through the first conducting wire and a second axis normal to the magnetic shift register wire and through the second conducting wire.
摘要翻译： 一种将奥斯特德场施加到磁存储器件的装置包括第一金属层; 定位在第一金属层上的第一绝缘层; 位于所述第一绝缘层上的磁性移位寄存器线; 定位在磁移位寄存器线上的第二绝缘层; 位于所述第二绝缘层上的第二金属层; 位于所述第一金属层中并横向于所述磁性移位寄存器线延伸的第一导线; 以及位于第二金属层中并横向于磁性移位寄存器线延伸的第二导线。 第一导线相对于第二导线偏移，偏移由通常与磁移位寄存器导线垂直的第一轴与第一导线之间的距离和与磁移位寄存器线垂直的第二轴定义， 第二根导线。
-
公开(公告)号：US20140141530A1
公开(公告)日：2014-05-22
申请号：US13970764
申请日：2013-08-20
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , B82Y99/00 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C19/0808 , H01F1/0072 , H01F10/3263 , H01L29/0673 , H01L43/08
摘要： A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
摘要翻译： 存储器件包括耦合第一和第二纳米线的第一纳米线，第二纳米线和磁性隧道结器件。
-
公开(公告)号：US09553257B1
公开(公告)日：2017-01-24
申请号：US14949267
申请日：2015-11-23
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1659 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
摘要翻译： 技术涉及线性磁阻随机存取存储器（MRAM）装置。 线性磁性隧道结结构包括在自由层顶部的非磁性隧道势垒和非磁性隧道势垒顶部的参考层，其中线性磁性隧道结结构处于一条直线上。 底部触点通过柱空间彼此分离，而多个底部触点与线性磁性隧道结结构自对准，使得多个底部触点与线性磁性隧道结结构线并联。 底部触点邻接线性磁隧道结结构的底部。 通过使自由层的非导电部分隔离底部触点和自由层之间的各个界面来形成MRAM器件。 MRAM器件形成在线性磁隧道结结构的线中。
-
18.发明授权Injection pillar definition for line MRAM by a self-aligned sidewall transfer 有权注射柱定义通过自对准侧壁转移线MRAM公开(公告)号：US09299924B1
公开(公告)日：2016-03-29
申请号：US14753163
申请日：2015-06-29
CPC分类号： H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
摘要： A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.
摘要翻译： 技术涉及MRAM系统。 保形膜覆盖形成在上部材料中的沟槽。 上部材料覆盖基板中的导电岛。 选择性地蚀刻保形膜以在沟槽上留下侧壁。 侧壁被蚀刻成垂直的柱，其自对准并且直接位于下面的导电岛的顶部。 将填充材料沉积并平坦化以留下垂直柱的暴露顶部。 MTJ元件形成在填充材料的顶部和垂直柱的暴露的顶部。 将MTJ元件图案化成对应于垂直列的线，并且每条线具有与其中一个垂直列自对准的线MTJ元件。 线路MRAM器件通过将MTJ元件图案化成线。 线路MRAM设备中的每一个分别包括与一个垂直列自对准的线MTJ元件。
-
19.发明授权Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction 有权基于纳米线磁隧道结中的电流诱导畴壁运动的多位非易失性存储器公开(公告)号：US08934289B2
公开(公告)日：2015-01-13
申请号：US13689934
申请日：2012-11-30
CPC分类号： G11C11/1675 , B82Y99/00 , G11C7/1006 , G11C11/161 , G11C11/5607 , G11C19/0808 , G11C19/0841 , Y10S977/762
摘要： A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
摘要翻译： 提供了一种用于在畴壁纳米线磁性结装置中存储多个位的机制。 基于使用单畴壁的畴壁纳米线磁性结装置的电阻对多个位进行编码。 移动单畴壁以改变畴壁纳米线磁结装置的电阻以编码所选择的位。 检查电阻以确保其对应于所选位的预选电阻。 响应于对应于所选位的预选电阻的电阻，他选择的位被存储。 响应于不是所选位的预选电阻的电阻，单畴壁移动直到电阻对应于预选电阻。
-
公开(公告)号：US20140138610A1
公开(公告)日：2014-05-22
申请号：US13682063
申请日：2012-11-20
CPC分类号： H01L43/12 , B82Y10/00 , B82Y99/00 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C19/0808 , H01F1/0072 , H01F10/3263 , H01L29/0673 , H01L43/08
摘要： A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
-
-
-
-
-
-
-
-
-
搜索结果
30 条记录 (耗时 0.016 秒)