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    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION
    12.
    发明申请
    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION 有权
    使用金属硅化物形成的CMOS-MEMS集成

    公开(公告)号：US20170057813A1

    公开(公告)日：2017-03-02

    申请号：US14838237

    申请日：2015-08-27

    Applicant: InvenSense, Inc.

    Inventor： Jong Il SHIN ,  Peter SMEYS ,  Jongwoo SHIN

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  B81B7/0006 ,  B81B2207/012 ,  B81C2203/019 ,  B81C2203/036 ,  B81C2203/0792

    Abstract: A method and system for forming a MEMS device are disclosed. In a first aspect, the method comprises providing a conductive material over at least a portion of a top metal layer of a base substrate, patterning the conductive material and the at least a portion of the top metal layer, and bonding the conductive material with a device layer of a MEMS substrate via metal silicide formation. In a second aspect, the MEMS device comprises a MEMS substrate, wherein the MEMS substrate includes a handle layer, a device layer, and an insulating layer in between. The MEMS device further comprises a base substrate, wherein the base substrate includes a top metal layer and a conductive material over at least a portion of the top metal layer, wherein the conductive material is bonded with the device layer via metal silicide formation.

    Abstract translation: 公开了一种用于形成MEMS器件的方法和系统。 在第一方面，该方法包括在基底衬底的顶部金属层的至少一部分上提供导电材料，图案化导电材料和顶部金属层的至少一部分，以及将导电材料与 通过金属硅化物形成MEMS衬底的器件层。 在第二方面，MEMS器件包括MEMS衬底，其中MEMS衬底包括手柄层，器件层和其间的绝缘层。 MEMS器件还包括基底，其中基底衬底包括在顶部金属层的至少一部分上的顶部金属层和导电材料，其中导电材料通过金属硅化物形成与器件层结合。

    CMOS-MEMS-CMOS PLATFORM
    13.
    发明申请
    CMOS-MEMS-CMOS PLATFORM 有权
    CMOS-MEMS-CMOS平台

    公开(公告)号：US20160362293A1

    公开(公告)日：2016-12-15

    申请号：US14738745

    申请日：2015-06-12

    Applicant: InvenSense, Inc.

    Inventor： Peter SMEYS ,  Martin LIM

    IPC: B81B7/00

    CPC classification number: B81B7/007 ,  B81B2201/0207 ,  B81B2201/0214 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: A sensor chip combining a substrate comprising at least one CMOS circuit, a MEMS substrate and another substrate comprising at least one CMOS circuit in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first substrate with a first surface and a second surface comprising at least one CMOS circuit; a MEMS substrate with a first surface and a second surface; and a second substrate comprising at least one CMOS circuit. Where the first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the MEMS substrate. The second surface of the MEMS substrate is attached to the second substrate. The first substrate, the MEMS substrate, the second substrate and the packaging substrate are mechanically attached and provided with electrical inter-connects.

    Abstract translation: 公开了一种传感器芯片，其组合包括至少一个CMOS电路，MEMS基板和包括垂直堆叠的一个封装中的至少一个CMOS电路的另一基板的基板。 所述封装包括传感器芯片，还包括具有第一表面的第一基板和包括至少一个CMOS电路的第二表面; 具有第一表面和第二表面的MEMS衬底; 以及包括至少一个CMOS电路的第二衬底。 其中第一衬底的第一表面附接到封装衬底，并且第一衬底的第二表面附接到MEMS衬底的第一表面。 MEMS基板的第二表面附接到第二基板。 第一基板，MEMS基板，第二基板和封装基板机械地连接并设置有电连接。

    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE
    15.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE 有权
    CMOS-MEMS集成器件，其中包括在不同的控制压力下的多个CAVIITY和制造方法

    公开(公告)号：US20150129991A1

    公开(公告)日：2015-05-14

    申请号：US14603185

    申请日：2015-01-22

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/0023 ,  B81B7/0038 ,  B81B7/0041 ,  B81B7/02 ,  B81B2201/0228 ,  B81B2207/017 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785

    Abstract: An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    Abstract translation: 集成MEMS器件包括两个基板，其中第一和第二基板耦合在一起并且其间具有两个外壳。 第一和第二基板之一包括除气源层和去气阻挡层，以调节两个外壳内的压力。 该方法包括在基板上沉积和图案化除气源层和第一除气阻挡层，产生两个横截面。 在两个横截面之一中，除气源层的顶表面不被除气阻挡层覆盖，而在两个横截面中的另一个中，除气源层被封装在除气阻挡层中。 该方法还包括平行地沉积第二除气阻挡层并蚀刻第二除气阻挡层，使得第二除气阻挡层的间隔物留在除气源层的侧壁上。

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