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11.发明授权公开(公告)号：US07110932B2
公开(公告)日：2006-09-19
申请号：US10171121
申请日：2002-06-13
申请人： Joerg Berthold , Henning Lorch
发明人： Joerg Berthold , Henning Lorch
IPC分类号： G06F17/50 , G01R23/175 , G01R13/02
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00078 , H03K2005/00097
摘要： A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit. Also, to allow a safety margin to be obtained, the signal path replicas have additional circuit elements that further slow down the signal transit times on the signal path replicas. Further, the mean of the transit times on the signal path replicas is determined.
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公开(公告)号：US07932542B2
公开(公告)日：2011-04-26
申请号：US11860413
申请日：2007-09-24
申请人： Joerg Berthold , Winfried Kamp , Fritz Rothacher
发明人： Joerg Berthold , Winfried Kamp , Fritz Rothacher
IPC分类号： H01L27/118
CPC分类号： H01L27/0207 , H01L21/823807 , H01L27/11803 , H01L29/7843
摘要： A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.
摘要翻译： 一种制造集成电路的方法，包括布置多个单元以形成集成电路的所需平面图，其中每个单元包括至少一个晶体管，从平面图的多个单元形成多个电路组件，其中 每个电路组件包括至少一个小区，属于多个电路组成类型中的一个，并且基于小区所属的电路组件的电路组成类型，对每个小区的至少一个晶体管的沟道区域施加机械应力 。
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公开(公告)号：US07859421B2
公开(公告)日：2010-12-28
申请号：US12361259
申请日：2009-01-28
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译： 一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性 第一振荡器与第二振荡器的频率的电压依赖性不同，被配置为评估第一振荡器的频率的第一评估电路和被配置为评估第二振荡器的频率的第二评估电路，以及配置为比较第二振荡器的比较电路 基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出表示第一电位和第二电位之间的不允许电压变化的电压变化信号。
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公开(公告)号：US07400526B2
公开(公告)日：2008-07-15
申请号：US11427337
申请日：2006-06-28
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译： 存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换成第一状态 状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时， 电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流 电阻元件的第二端子，以便将电阻元件转换成第二端子 状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。
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公开(公告)号：US20070002619A1
公开(公告)日：2007-01-04
申请号：US11427339
申请日：2006-06-28
IPC分类号： G11C11/34
CPC分类号： G11C14/009 , G11C13/0004
摘要： The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for non-volatile saving of the stored information and a means for saving the information in the resistance element. A means for retrieving the saved information is additionally present.
摘要翻译： 非易失性存储单元具有用于存储二进制信息项的易失性存储装置。 此外，存储单元仅包括用于非易失性地存储信息的单个可编程电阻元件和用于将信息保存在电阻元件中的装置。 另外存在用于检索保存的信息的装置。
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公开(公告)号：US08183636B2
公开(公告)日：2012-05-22
申请号：US13072805
申请日：2011-03-28
申请人： Joerg Berthold , Christian Pacha , Klaus Arnim Von
发明人： Joerg Berthold , Christian Pacha , Klaus Arnim Von
IPC分类号： H01L21/84 , H01L21/8238
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor coupled between a second node and the ground voltage; a first n-channel access transistor coupled between a first bit line and the first node of the first inverter, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor; and a second n-channel access transistor coupled between a second bit line and the second node of the second inverter, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor.
摘要翻译： 一个或多个实施例涉及静态随机存取存储器单元，包括：第一反相器，包括耦合在第一节点和地电压之间的第一n沟道下拉晶体管; 第二反相器，包括耦合在第二节点和地电压之间的第二n沟道下拉晶体管; 耦合在第一位线和第一反相器的第一节点之间的第一n沟道存取晶体管，第一n沟道存取晶体管的鳍具有比第一n沟道下拉的鳍低的电荷载流子迁移率 晶体管 以及耦合在所述第二反相器的第二位线和所述第二节点之间的第二n沟道存取晶体管，所述第二n沟道存取晶体管的鳍具有比所述第二n沟道下拉沿的鳍更低的电荷载流子迁移率， 下降晶体管。
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17.发明申请Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement 审中-公开多翅片组件布置和制造多鳍组件布置的方法公开(公告)号：US20080283925A1
公开(公告)日：2008-11-20
申请号：US12124369
申请日：2008-05-21
IPC分类号： H01L27/088 , H01L21/82
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/785
摘要： In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another.
摘要翻译： 在第一实施例中，多翅片部件布置具有多个多翅片部件部分布置。 多片组件部分布置中的每一个具有多个电子部件，该电子部件具有多鳍结构。 至少一个多翅片部件部分布置具有至少一个虚拟结构，在形成于至少一个多翅片部件部分布置中的至少两个电子部件之间形成至少一个虚拟结构。 虚拟结构形成为使得形成在多翅片部件部分布置中的电子部件的电特性彼此适配。
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公开(公告)号：US5371423A
公开(公告)日：1994-12-06
申请号：US107960
申请日：1993-08-17
IPC分类号： H03K17/567 , H03K17/081 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0944 , H03K19/02
CPC分类号： H03K17/08112 , H03K19/00307 , H03K19/09429 , H03K19/09448
摘要： A tri-state capable driver circuit or totem pole circuit is formed in BiCMOS technology and includes a selection circuit, first and second drive circuits, and first and second bipolar transistors. A short circuit unit is connected between the base and the emitter of the first bipolar transistor to prevent excessively high inhibit voltages across the base-emitter junction of the first bipolar transistor. The operation of the short circuit unit depends upon signals received at the tri-state activation input.
摘要翻译： 具有三态的驱动器电路或图腾柱电路以BiCMOS技术形成，包括选择电路，第一和第二驱动电路以及第一和第二双极晶体管。 短路单元连接在第一双极晶体管的基极和发射极之间，以防止跨越第一双极晶体管的基极 - 发射极结的过高的抑制电压。 短路单元的操作取决于在三态激活输入端接收到的信号。
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19.发明授权公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译： 本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率 晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道 存取晶体管耦合在第二反相器的第二位线和第二节点之间。
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公开(公告)号：US20090189702A1
公开(公告)日：2009-07-30
申请号：US12361259
申请日：2009-01-28
IPC分类号： H03K3/03
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译： 一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性 第一振荡器与第二振荡器的频率的电压依赖性不同，第一评估电路，被配置为评估第一振荡器的频率，以及第二评估电路，被配置为评估第二振荡器的频率;以及比较电路，被配置为比较 基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出指示第一电位和第二电位之间的不允许电压变化的电压变化信号。
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