公开(公告)号：US08916337B2

公开(公告)日：2014-12-23

申请号：US13402068

申请日：2012-02-22

申请人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

IPC分类号： G03F7/26

CPC分类号： H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

摘要： A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

摘要翻译： 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

公开(公告)号：US20130216776A1

公开(公告)日：2013-08-22

申请号：US13402068

申请日：2012-02-22

申请人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

IPC分类号： B32B3/00 ,  G03F7/20

CPC分类号： H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

摘要： A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

摘要翻译： 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

公开(公告)号：US20120198403A1

公开(公告)日：2012-08-02

申请号：US13018551

申请日：2011-02-01

申请人： John C. Arnold ,  Catherine Labelle

发明人： John C. Arnold ,  Catherine Labelle

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L21/76808 ,  H01L22/12 ,  H01L22/20

摘要： A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

摘要翻译： 用于改变半导体晶片上的设计特征的深度的方法。 通风口根据设计要求形成。 也可以在相对于设计特征的位置放置不起作用的通孔。 在形成通孔之后，使半导体晶片经历灰化处理，随后施加有机平坦化层。 然后形成设计特征。 如果设计特征的深度不符合设计要求，则可以通过改变灰化条件，有机平坦化层的选择和/或无功能和/或功能的通过放置来处理另一半导体晶片以满足设计要求。 在单个半导体晶片上具有各种深度的设计特征可以用单个光刻工艺形成。

公开(公告)号：US08084329B2

公开(公告)日：2011-12-27

申请号：US12693629

申请日：2010-01-26

申请人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

发明人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

摘要翻译： 在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间​​的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

公开(公告)号：US07776695B2

公开(公告)日：2010-08-17

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20070267618A1

公开(公告)日：2007-11-22

申请号：US11435594

申请日：2006-05-17

申请人： Shoaib Zaidi ,  John C. Arnold

发明人： Shoaib Zaidi ,  John C. Arnold

IPC分类号： H01L29/02 ,  H01L29/04

CPC分类号： H01L45/1691 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144

摘要： A phase change memory cell includes a first spacer electrically coupled to a first electrode and to a second spacer. The first spacer includes a planar base contacting the first electrode and a wall extending from the planar base. The second spacer is electrically coupled between a second electrode and the wall of the first spacer. The phase change memory cell is formed at a boundary where the wall of the first spacer contacts the second spacer.

摘要翻译： 相变存储单元包括电耦合到第一电极和第二间隔物的第一间隔件。 第一间隔件包括接触第一电极的平面底座和从平面底座延伸的壁。 第二间隔件电连接在第二电极和第一间隔件的壁之间。 相变存储单元形成在第一间隔件的壁与第二间隔件接触的边界处。

公开(公告)号：US20070158753A1

公开(公告)日：2007-07-12

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

公开(公告)号：US06500315B1

公开(公告)日：2002-12-31

申请号：US09631400

申请日：2000-08-03

申请人： Valli Arunachalam ,  Peter L. G. Ventzek ,  Dean J. Denning ,  John C. Arnold

发明人： Valli Arunachalam ,  Peter L. G. Ventzek ,  Dean J. Denning ,  John C. Arnold

IPC分类号： C23C1600

CPC分类号： H01J37/321 ,  C23C14/352 ,  C23C14/358 ,  H01L21/02112 ,  H01L21/02266 ,  H01L21/31629

摘要： A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

摘要翻译： 公开了一种在衬底上形成层的方法和装置。 根据一个实施例，将衬底（901）放置在包括线圈（16）和屏蔽（14）的腔室（30）中，其中线圈和屏蔽件通过隔离/支撑构件（32）电隔离， 具有与所述线圈的表面基本相邻的第一表面（321），并具有与所述屏蔽件的表面基本相邻的第二表面（322）。 然后在衬底（901）上沉积一层（1002,1102）。

公开(公告)号：US5683548A

公开(公告)日：1997-11-04

申请号：US605697

申请日：1996-02-22

申请人： Michael J. Hartig ,  John C. Arnold

发明人： Michael J. Hartig ,  John C. Arnold

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23C16/507 ,  C23F4/00 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/00

CPC分类号： H01J37/3244 ,  C23C16/507 ,  H01J37/321 ,  Y10S438/935

摘要： An inductively coupled plasma reactor and method for processing a semiconductor wafer (28). The inductively coupled plasma reactor (10) includes a plasma source (16) having a plurality of channels (38, 44) in which processing gases are independently supplied to each channel. A gas supply system (20) includes a plurality of gas feed lines (34, 35, 36) each capable of supplying an individual flow rate and gas composition to the plurality of channels (38, 44) in the plasma source (16). Each channel is surrounded by an independently powered RF coil (54, 56), such that the plasma density can be varied within each channel (38, 44) of the plasma source (16). In operation, a material layer (66) overlying a semiconductor wafer (28) is either uniformly etched or deposited by localized spatial control of the plasma characteristics at each location (64) across the semiconductor wafer (28).

摘要翻译： 一种用于处理半导体晶片（28）的电感耦合等离子体反应器和方法。 电感耦合等离子体反应器（10）包括具有多个通道（38,44）的等离子体源（16），其中处理气体被独立地提供给每个通道。 气体供应系统（20）包括多个气体供给管线（34,35,36），每个气体供给管线能够将等离子体源（16）中的多个通道（38,44）提供单独的流量和气体组成。 每个通道由独立供电的RF线圈（54,56）包围，使得等离子体密度可以在等离子体源（16）的每个通道（38,44）内变化。 在操作中，覆盖半导体晶片（28）的材料层（66）通过半导体晶片（28）上的每个位置（64）处的等离子体特性的局部空间控制被均匀蚀刻或沉积。