公开(公告)号：US08916337B2

公开(公告)日：2014-12-23

申请号：US13402068

申请日：2012-02-22

申请人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

IPC分类号： G03F7/26

CPC分类号： H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

摘要： A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

摘要翻译： 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

公开(公告)号：US20130216776A1

公开(公告)日：2013-08-22

申请号：US13402068

申请日：2012-02-22

申请人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

IPC分类号： B32B3/00 ,  G03F7/20

CPC分类号： H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

摘要： A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

摘要翻译： 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

公开(公告)号：US08470711B2

公开(公告)日：2013-06-25

申请号：US12952248

申请日：2010-11-23

申请人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

IPC分类号： H01L21/44

CPC分类号： H01L23/00 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

摘要翻译： 用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。 用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露 底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

公开(公告)号：US20120126358A1

公开(公告)日：2012-05-24

申请号：US12952248

申请日：2010-11-23

申请人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

发明人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

IPC分类号： H01L21/311 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/00 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

摘要翻译： 用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。 用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露 底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

公开(公告)号：US20090032491A1

公开(公告)日：2009-02-05

申请号：US11833301

申请日：2007-08-03

申请人： Veeraraghavan S. Basker ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian

发明人： Veeraraghavan S. Basker ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian

IPC分类号： H01B13/00 ,  B32B3/10

CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L2221/1026 ,  H01L2221/1031 ,  Y10T428/24273

摘要： Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes.

摘要翻译： 公开了形成用于集成电路（IC）芯片的导电元件和相关结构的方法。 该方法的一个实施例可以包括形成其中具有图案的第一牺牲层用于第一介电层以围绕导电元件; 在所述图案化的第一牺牲层内形成所述第一介电层; 去除图案化的第一牺牲层，留下第一介电层; 以及在由图案化的第一牺牲层腾出的空间中形成导电元件。 该方法防止在蚀刻和剥离/清洗过程中对低介电常数电介质层造成的损坏。

公开(公告)号：US20140035142A1

公开(公告)日：2014-02-06

申请号：US13562953

申请日：2012-07-31

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US08835305B2

公开(公告)日：2014-09-16

申请号：US13562953

申请日：2012-07-31

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

IPC分类号： H01L21/4763 ,  H01L23/12 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US08946866B2

公开(公告)日：2015-02-03

申请号：US13490239

申请日：2012-06-06

申请人： Charles W. Koburger, III ,  Steven J. Holmes ,  David V. Horak ,  Kurt R. Kimmel ,  Karen E. Petrillo ,  Christopher F. Robinson

发明人： Charles W. Koburger, III ,  Steven J. Holmes ,  David V. Horak ,  Kurt R. Kimmel ,  Karen E. Petrillo ,  Christopher F. Robinson

IPC分类号： H01L29/06 ,  G03F7/20

CPC分类号： G03F7/70691 ,  G03F7/70341 ,  G03F7/70808

摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

摘要翻译： 提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。 这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。 前表面是物品的主要表面。 具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。 以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦， 周缘连接到内边缘。

公开(公告)号：US20140061930A1

公开(公告)日：2014-03-06

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

公开(公告)号：US20130328208A1

公开(公告)日：2013-12-12

申请号：US13490542

申请日：2012-06-07

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。