公开(公告)号：US5157280A

公开(公告)日：1992-10-20

申请号：US655877

申请日：1991-02-13

申请人： John F. Schreck ,  Phat C. Truong ,  Chirag Desai

发明人： John F. Schreck ,  Phat C. Truong ,  Chirag Desai

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  H01L27/02 ,  H03K17/693

CPC分类号： H03K17/693 ,  G11C16/12 ,  H01L27/0248 ,  H03K2217/0018

摘要： A switching circuit for selectively coupling a first power supply to a power bus includes a first input terminal for connection to the first power supply and a means for coupling said first input terminal to a first node. A first transistor has a first source/drain region coupled to the first node and a second source/drain region coupled to the power bus. The first transistor is on in response to a first control signal applied to its gate to couple the first node to the power bus. A bias circuit is coupled to the substrate of the first transistor to prevent forward biasing of a junction between its substrate and its second source/drain region when the first transistor is on.

公开(公告)号：US5151880A

公开(公告)日：1992-09-29

申请号：US450808

申请日：1989-12-14

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C16/20

CPC分类号： G11C16/20

摘要： Apparatus for determining the field position (00, 01, 10, 11) of an integrated circuit (18) within a reticle area (12) which contains a plurality of such integrated circuits (14-20) includes a plurality of memory cells (76, 80) formed within the integrated circuit (18) for encoding the field position. Circuitry (40, 94, 100, 104, 106) is provided for reading the states of the memory cells to ascertain the field position.

摘要翻译： 用于确定包含多个这种集成电路（14-20）的标线片区域（12）内的集成电路（18）的场位置（00,01,10,11）的装置包括多个存储单元（76 ，80）形成在集成电路（18）内，用于对场位置进行编码。 电路（40,94,100,104,106）被提供用于读取存储器单元的状态以确定场位置。

公开(公告)号：US4750024A

公开(公告)日：1988-06-07

申请号：US830160

申请日：1986-02-18

申请人： John F. Schreck

发明人： John F. Schreck

IPC分类号： H01L21/8247 ,  H01L21/762 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/40 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L27/115 ,  H01L21/76216 ,  H01L29/7885

摘要： An electrically programmable read only memory device formed in a face of a semiconductor substrate of a first conductivity type which includes a pair of spaced apart thick oxide isolation regions defining an elongated channel of the substrate therebetween. A floating gate of conductive material overlies a portion of one of the isolation regions and a first portion of the elongated channel being separated from the oxide isolation and channel regions by an insulator layer. A control layer of conductive material extends over the channel and the floating gate separated from both of the latter by an insulator layer. Buried diffused regions are located below each oxide isolation region.

摘要翻译： 一种电可编程只读存储器件，形成在第一导电类型的半导体衬底的表面上，该第一导电类型的半导体衬底包括一对间隔开的厚度的氧化物隔离区域，该氧化物隔离区域限定了衬底之间的细长通道。 导电材料的浮栅覆盖在隔离区之一的一部分上，并且细长通道的第一部分通过绝缘体层与氧化物隔离和沟道区分离。 导电材料的控制层在沟道上延伸，浮动栅极通过绝缘体层与后者分离。 掩埋扩散区位于每个氧化物隔离区的下方。

公开(公告)号：US08519767B2

公开(公告)日：2013-08-27

申请号：US13333850

申请日：2011-12-21

申请人： Eric Booth ,  Tyler Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

发明人： Eric Booth ,  Tyler Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

IPC分类号： H03K3/00

CPC分类号： H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

公开(公告)号：US07106637B2

公开(公告)日：2006-09-12

申请号：US10754658

申请日：2004-01-08

申请人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

发明人： Simon J. Lovett ,  Cliff Zitlaw ,  Brian M. Shirley ,  Roger D. Norwood ,  John F. Schreck

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

公开(公告)号：US5365486A

公开(公告)日：1994-11-15

申请号：US991233

申请日：1992-12-16

申请人： John F. Schreck

发明人： John F. Schreck

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/3431 ,  G11C16/10 ,  G11C16/3418

摘要： A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been programmed, then the next memory cell is read (46). If it is initially determined that the cell has not been programmed (44), then the particular memory cell is read at a lowered control gate voltage (48). It is then finally determined whether the cell has been programmed (50). If it is determined that the cell has not been programmed, then the next cell is read (46). If it is determined that the cell has been programmed (50), then the memory is refreshed (52). After refresh, the next memory cell is read (46).

摘要翻译： 提供了一种用于快速EEPROM刷新的方法和装置，其中在升高的控制栅极电压（42）下读取特定存储单元的控制栅极。 接下来确定单元格是否已被编程（44）。 如果单元已被编程，则读取下一个存储单元（46）。 如果最初确定单元未被编程（44），则在降低的控制栅极电压（48）处读取特定存储单元。 然后最后确定单元格是否已被编程（50）。 如果确定单元未被编程，则读取下一个单元（46）。 如果确定单元格已被编程（50），则刷新存储器（52）。 刷新后，读取下一个存储单元（46）。

公开(公告)号：US4858187A

公开(公告)日：1989-08-15

申请号：US150861

申请日：1988-02-01

申请人： John F. Schreck

发明人： John F. Schreck

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10

摘要： A programming implementation circuit for use in programming a floating-gate, avalanche-injection, metal-oxide-semiconductor integrated-circuit memory cell. The circuit is comprised of programming control means, a decoder switching means and an enabling means. A current-limiting input voltage is transmitted by the decoder switching means to the programming control means when the circuit is placed in one state by the enabling means, causing the control means to limit current during programming. When the cicuit is placed in a second state by the enabling means, the programming control means is deactivated and the bit line of the memory circuit is connected to a sense amplifier.

摘要翻译： 一种用于编程浮栅，雪崩注入，金属氧化物半导体集成电路存储单元的编程实现电路。 电路由编程控制装置，解码器切换装置和启用装置组成。 当通过使能装置将电路置于一个状态时，解码器切换装置将限流输入电压传送到编程控制装置，使得控制装置在编程期间限制电流。 当通过启用装置将c子置于第二状态时，编程控制装置被去激活，并且存储器电路的位线连接到读出放大器。

公开(公告)号：US4797857A

公开(公告)日：1989-01-10

申请号：US850636

申请日：1986-04-11

申请人： John F. Schreck ,  Timmie M. Coffman ,  David D. Wilmoth

发明人： John F. Schreck ,  Timmie M. Coffman ,  David D. Wilmoth

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C7/00

CPC分类号： G11C16/24 ,  G11C7/12

摘要： A discharge circuit for discharging bit lines of an array of semiconductor memory cells in which the array of bit lines are biased from a single bias line. The discharge circuit includes a discharge switch coupled to the bias line for discharging the bit lines and the bias line and a control circuit coupled to the discharge switch operative to turn on the discharge switch in response to the voltage on the bias line rising above a first predetermined level and then to turn off the discharge switch in response to the voltage on the bias line falling below a second predetermined level.

摘要翻译： 一种放电电路，用于对其中位线阵列从单个偏置线偏置的半导体存储器单元阵列的位线进行放电。 放电电路包括耦合到偏置线用于对位线和偏置线进行放电的放电开关，以及耦合到放电开关的控制电路，用于响应于偏置线上的电压升高到高于第一 然后响应于偏压线上的电压下降到第二预定水平以关闭放电开关。

公开(公告)号：US4723225A

公开(公告)日：1988-02-02

申请号：US786981

申请日：1985-10-15

申请人： Jeffrey K. Kaszubinski ,  Debra J. Dolby ,  Timmie M. Coffman ,  John F. Schreck

发明人： Jeffrey K. Kaszubinski ,  Debra J. Dolby ,  Timmie M. Coffman ,  John F. Schreck

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/10

摘要： An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.2 is established at the junction of the second circuit element and the module floating gate transistor. Comparing means compares voltages V.sub.1 and V.sub.2 and adjusts the gate voltage V.sub.3 of the module programming control transistor so as to make the voltage V.sub.2 equal to voltage V.sub.1 and applies voltage V.sub.3 to the gates of the array programming control transistors. Since the transistor in the reference path is both electrically and geometrically the same as that in the second leg across which the voltage developed is compared, and is made by the same process, the current in the second leg will be substantially the same as that in the reference leg. Moreover, since the array floating gate transistors are also made by the same process as is the module floating gate transistor and the programming control and ground select transistors are also identical, by feeding the voltage V.sub.3 to array control transistors substantially the same current will flow through a selected array transistor as flows through both the reference current path and the second current leg.

摘要翻译： 一种具有可编程半导体浮置栅极晶体管阵列的类型的电可编程半导体存储器件，其组合耦合在相关联的源极和漏极线之间，阵列编程控制晶体管和接地选择晶体管，其耦合到每个漏极和源极线 。 编程模式中的每个选择的浮栅晶体管与高电压Vpp和地电位之间的控制和接地选择晶体管串联。 与第一导电电路元件串联的电阻元件建立在电阻元件和电路元件的结处产生电压V1的参考电流。 在第二电流支路中，第二导通电路元件，偏置于导通状态的模块浮栅晶体管和模块控制晶体管都连接在Vpp和地之间，使得在第二电路元件和 模块浮栅晶体管。 比较装置比较电压V1和V2并调节模块编程控制晶体管的栅极电压V3，以使电压V2等于电压V1，并将电压V3施加到阵列编程控制晶体管的栅极。 由于参考路径中的晶体管的电学和几何尺寸与第二支腿相同，因此，通过相同的工艺制造电压，并且通过相同的工艺制造电压，第二支脚中的电流将基本上与 参考腿 此外，由于阵列浮栅晶体管也是通过与模块浮栅晶体管相同的工艺制成的，并且编程控制和接地选择晶体管也相同，通过将电压V3馈送到阵列控制晶体管，基本上相同的电流将流过 所选择的阵列晶体管流过参考电流路径和第二电流支路。

公开(公告)号：US08181086B2

公开(公告)日：2012-05-15

申请号：US13086137

申请日：2011-04-13

申请人： John F. Schreck ,  Todd A. Dauenbaugh

发明人： John F. Schreck ,  Todd A. Dauenbaugh

IPC分类号： H03M13/00

CPC分类号： G06F11/106 ,  G06F11/1056 ,  G06F11/1076

摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.

摘要翻译： 各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。 实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器 的连续时钟周期。 错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。