公开(公告)号：US06642565B2

公开(公告)日：2003-11-04

申请号：US09935624

申请日：2001-08-23

申请人： Emmerich Bertagnolli ,  Till Schlösser ,  Josef Willer

发明人： Emmerich Bertagnolli ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L28/82

摘要： A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

公开(公告)号：US06403440B1

公开(公告)日：2002-06-11

申请号：US09285897

申请日：1999-04-08

申请人： Emmerich Bertagnolli ,  Josef Willer

发明人： Emmerich Bertagnolli ,  Josef Willer

IPC分类号： H01L2120

CPC分类号： H01L28/87 ,  H01L27/10852 ,  H01L28/88

摘要： A method for fabricating a stacked capacitor in a semiconductor configuration, in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The semiconductor configuration having one electrode of a stacked capacitor produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. After the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed, with the result that the electrode has the same conductivity type as the terminal region and no pn junction occurs between the electrode and terminal region.

摘要翻译： 一种用于制造半导体构造的层叠电容器的方法，其中层叠电容器的一个电极经由第一导电类型的端子区域连接到晶体管的源极或漏极。 半导体结构具有通过利用掺杂到不同程度的第二导电类型的半导体层的不同蚀刻速率而产生的堆叠电容器的一个电极。 在层叠电容器的一个电极的蚀刻之后，执行在蚀刻操作之后保留的半导体层的掺杂反转到第一导电类型，结果是电极具有与端子区域相同的导电类型，并且没有pn结 发生在电极和端子区域之间。

公开(公告)号：US06194765B1

公开(公告)日：2001-02-27

申请号：US09313433

申请日：1999-05-17

申请人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

发明人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

摘要翻译： 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

公开(公告)号：US07049651B2

公开(公告)日：2006-05-23

申请号：US10715142

申请日：2003-11-17

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

摘要翻译： 电荷捕获层包括在源极和漏极结上方的两个条带。 选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。 通过将热孔单独注入热孔进行两位存储来执行编程。

公开(公告)号：US06627940B1

公开(公告)日：2003-09-30

申请号：US09937838

申请日：2002-02-05

申请人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

发明人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

摘要翻译： 存储单元阵列包括形成平行的第一和第二沟槽的衬底。 晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。 与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。 相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。 在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。 绝缘空间横向与字线连接。 导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

申请人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

发明人： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US5347696A

公开(公告)日：1994-09-20

申请号：US164719

申请日：1993-12-10

申请人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

发明人： Josef Willer ,  Hermann Wendt ,  Hans Reisinger

IPC分类号： C23F4/00 ,  H01G4/30 ,  H01L21/822 ,  H01L27/04 ,  H01G4/10

CPC分类号： H01G4/306 ,  Y10T29/435

摘要： For manufacturing a multi-layer capacitor, a layer structure (2, 3, 4) is applied onto a substrate (1), said layer structure comprising conductive layers (2, 4) and dielectric layers (3) in alternation and successive conductive layers (2, 4) therein being respectively formed of one of two different materials which are selectively etchable relative to one another. Two openings (6, 8) are produced in the layer structure (2, 3, 4), whereby under-etchings (21, 41 ) are formed in the first opening (6) by selective etching of the one material and are formed in the second opening (8) by selective etching of the other material, so that only the conductive layers (2, 4) of the non-etched material respectively adjoin contacts (91, 92) introduced into the openings (6, 8).

摘要翻译： 为了制造多层电容器，将层结构（2,3,4）施加到衬底（1）上，所述层结构交替包括导电层（2,4）和电介质层（3），并且连续导电层 （2,4）分别由可相对于彼此选择性地蚀刻的两种不同材料之一形成。 在层结构（2,3,4）中产生两个开口（6,8），由此通过选择性蚀刻该一种材料形成在第一开口（6）中的下蚀刻（21,41），并形成在 所述第二开口（8）通过选择性蚀刻所述另一材料，使得仅所述非蚀刻材料的所述导电层（2,4）分别与引入所述开口（6,8）的触点（91,92）相邻。

公开(公告)号：US07402490B2

公开(公告)日：2008-07-22

申请号：US11253939

申请日：2005-10-19

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

公开(公告)号：US20060091448A1

公开(公告)日：2006-05-04

申请号：US11253939

申请日：2005-10-19

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

公开(公告)号：US06518613B2

公开(公告)日：2003-02-11

申请号：US09968304

申请日：2001-10-01

申请人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

发明人： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

摘要翻译： 存储单元的MOS晶体管和与其连接的位线设置在基板的第一表面上。 存储单元的电容器设置在基板的第二表面上，第二表面与第一表面相对。 接触件设置在衬底中并将电容器连接到MOS晶体管。