公开(公告)号：US06821863B2

公开(公告)日：2004-11-23

申请号：US10348150

申请日：2003-01-21

申请人： Martin Popp ,  Dietmar Temmler ,  Kristin Schupke ,  Uwe Schilling ,  Kerstin Pomplun

发明人： Martin Popp ,  Dietmar Temmler ,  Kristin Schupke ,  Uwe Schilling ,  Kerstin Pomplun

IPC分类号： H01L2176

CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/1087

摘要： A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

摘要翻译： 半导体元件具有形成在单晶硅衬底中的空腔。 至少在上衣领区中，空腔的壁被覆盖层覆盖，然后使用选择性外延生长法将覆盖层施加到硅衬底的表面。 因此在该过程中覆盖空腔。 该方法物理上简单，可以经济有效地进行。 特别地，可以使用所描述的方法来在DRAM存储器的制造期间在高温处理之前覆盖沟槽，并且在高温处理之后再次打开沟槽，以便提供沟槽电容器 。

公开(公告)号：US20130187031A1

公开(公告)日：2013-07-25

申请号：US13355814

申请日：2012-01-23

申请人： Martin Popp ,  Beat De Coi

发明人： Martin Popp ,  Beat De Coi

IPC分类号： H01J40/14 ,  H01L31/18 ,  B82Y20/00

CPC分类号： G01S17/36 ,  G01S7/4863 ,  G01S17/89

摘要： A sensor apparatus including at least one analog and one digital circuit component and an analog/digital converter for converting analog signals of the analog circuit component into digital signals for the digital circuit component, and vice versa, wherein the analog circuit component and the digital circuit components include at least one module for electronically implementing a function, and wherein one of the modules of the analog circuit component is embodied as a sensor device for detecting optical radiation and one of the modules of the digital circuit component is embodied as a signal processing device for processing digital signals. In order to enable improved integration into application-based sensor devices, the circuit components including the analog/digital converter are integrated as an integrated circuit in a chip and the chip is manufactured as a semiconductor structure using 1-poly technology.

摘要翻译： 一种传感器装置，包括至少一个模拟和一个数字电路部件和用于将模拟电路部件的模拟信号转换为数字电路部件的数字信号的模/数转换器，反之亦然，其中模拟电路部件和数字电路 组件包括用于电子地实现功能的至少一个模块，并且其中模拟电路部件的模块之一被实现为用于检测光辐射的传感器装置，并且数字电路部件的模块之一被实现为信号处理装置 用于处理数字信号。 为了能够改进集成到基于应用的传感器装置中，包括模拟/数字转换器的电路部件作为集成电路集成在芯片中，并且该芯片被制造为使用1-聚技术的半导体结构。

公开(公告)号：US20100097835A1

公开(公告)日：2010-04-22

申请号：US12252826

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： G11C5/06 ,  G11C11/24

CPC分类号： G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

摘要翻译： 包括存储单元阵列的集成电路包括有源区线，位线，所述位线被布置成使得单独的位线与多个有源区域线相交以分别形成位线接触，位线布置在位线间距处，字线 被布置为使得单个字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，字线以字线间距排列，其中相邻位线接触，每个 连接到有源区线之一，与不同的位线连接，位线间距与字线间距不同。

公开(公告)号：US20100096669A1

公开(公告)日：2010-04-22

申请号：US12252853

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： H01L29/76 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

摘要翻译： 包括存储单元阵列的集成电路包括沿着并行有源区域线，位线布置的晶体管，位线被布置成使得各个相互交叉的多个有源区域线分别形成位线接触，位线形成为 摆动的线条，字线被布置成使得字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，其中相邻的位线接触，其中每一个连接到一个 的有源面积线与不同的位线连接。

公开(公告)号：US07700983B2

公开(公告)日：2010-04-20

申请号：US11300853

申请日：2005-12-15

申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

公开(公告)号：US07642572B2

公开(公告)日：2010-01-05

申请号：US11735164

申请日：2007-04-13

申请人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

发明人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

IPC分类号： H01L27/108

CPC分类号： H01L27/10817 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

摘要翻译： 公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。 一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。 位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。 相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。 以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

公开(公告)号：US07274060B2

公开(公告)日：2007-09-25

申请号：US11152793

申请日：2005-06-15

申请人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

发明人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC分类号： H01L21/8244 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

摘要： A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

摘要翻译： 存储单元阵列包括具有存储电容器和存取晶体管的存储单元。 存取晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线上方。

公开(公告)号：US20070138523A1

公开(公告)日：2007-06-21

申请号：US11300853

申请日：2005-12-15

申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

IPC分类号： H01L29/94 ,  H01L21/8244

CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。

公开(公告)号：US20070032033A1

公开(公告)日：2007-02-08

申请号：US11493931

申请日：2006-07-27

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L21/20

CPC分类号： H01L27/10867

摘要： A connecting structure connects a storage electrode of a trench capacitor and a selection transistor that are at least partially formed in a semiconductor substrate. The connecting structure includes a portion of an intermediate layer disposed adjacent to a surface of the storage electrode, and an electrically conducting material disposed adjacent to the intermediate layer and electrically connected to a semiconductor substrate surface portion adjacent to the selection transistor, wherein a part of the connecting structure is disposed above the semiconductor substrate surface so as to be adjacent to a horizontal substrate surface portion.

摘要翻译： 连接结构连接沟槽电容器的存储电极和至少部分地形成在半导体衬底中的选择晶体管。 所述连接结构包括邻近所述存储电极的表面设置的中间层的一部分，以及与所述中间层相邻设置并电连接到与所述选择晶体管相邻的半导体衬底表面部分的导电材料，其中， 连接结构设置在半导体衬底表面上方以与水平衬底表面部分相邻。

公开(公告)号：US20070032032A1

公开(公告)日：2007-02-08

申请号：US11356459

申请日：2006-02-17

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L21/20

CPC分类号： H01L27/10867

摘要： A method for manufacturing a surface strap connection between a trench capacitor and a selection transistor includes providing a masking material on a surface of a semiconductor substrate in areas where no trench capacitors have been formed. An undoped semiconductor layer having vertical and horizontal areas is applied. An oblique ion implantation is performed such that a vertical area of the semiconductor layer on which the connecting structure is to be formed is not doped. After removal of the undoped portion of the semiconductor layer, the exposed portion of the masking material is laterally etched, one part of the substrate surface is exposed, and the doped part of the semiconductor layer is removed. An electrically conducting connection material is applied so that an electrical contact exists between the exposed portion of the substrate surface and the storage electrode.

摘要翻译： 用于制造沟槽电容器和选择晶体管之间的表面带连接的方法包括在没有形成沟槽电容器的区域中在半导体衬底的表面上提供掩模材料。 施加具有垂直和水平面积的未掺杂的半导体层。 进行倾斜离子注入，使得要在其上形成连接结构的半导体层的垂直面积不被掺杂。 在去除半导体层的未掺杂部分之后，屏蔽材料的暴露部分被横向蚀刻，衬底表面的一部分被暴露，并且去除半导体层的掺杂部分。 施加导电连接材料，使得在基板表面的暴露部分和存储电极之间存在电接触。