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    Memory system
    11.
    发明授权
    Memory system 有权

    公开(公告)号：US11626167B2

    公开(公告)日：2023-04-11

    申请号：US17131026

    申请日：2020-12-22

    Applicant: KIOXIA CORPORATION

    Inventor： Masanobu Shirakawa ,  Tsukasa Tokutomi ,  Marie Takada

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/1157

    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

    Semiconductor memory device
    12.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11626142B2

    公开(公告)日：2023-04-11

    申请号：US17500066

    申请日：2021-10-13

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa ,  Takuya Futatsuyama

    IPC: G11C5/06 ,  G11C7/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

    MEMORY SYSTEM
    13.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210295931A1

    公开(公告)日：2021-09-23

    申请号：US17005273

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Marie Takada ,  Masanobu Shirakawa

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

    Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.

    MEMORY SYSTEM
    14.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20250054564A1

    公开(公告)日：2025-02-13

    申请号：US18795818

    申请日：2024-08-06

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa ,  Naomi Takeda ,  Ryo Yamaki ,  Shogo Muto ,  Hideki Yamada

    IPC: G11C29/52 ,  G11C29/02

    Abstract: According to one embodiment, a memory system includes a memory chip and a memory controller. A first cell unit and a second cell unit are classified into a first group. A third cell unit is classified into a second group. The memory controller is configured to use a first correction amount of a read voltage when data of the first group is read and to use a second correction amount of the read voltage when data of the second group is read. When a time difference from a write operation of the first cell unit to the write operation of the second cell unit exceeds a reference value, the memory controller is configured to change a boundary position between the first group and the second group to between the first cell unit and the second cell unit, and to classify the second cell unit into the second group.

    Memory system
    16.
    发明授权
    Memory system 有权

    公开(公告)号：US12001687B2

    公开(公告)日：2024-06-04

    申请号：US17942541

    申请日：2022-09-12

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller. The memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition.

    Memory system
    18.
    发明授权
    Memory system 有权

    公开(公告)号：US11698834B2

    公开(公告)日：2023-07-11

    申请号：US17718969

    申请日：2022-04-12

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Marie Takada

    IPC: G06F11/00 ,  G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

    CPC classification number: G06F11/1068 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

    Memory system
    19.
    发明授权
    Memory system 有权

    公开(公告)号：US11636914B2

    公开(公告)日：2023-04-25

    申请号：US17471539

    申请日：2021-09-10

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/50 ,  G11C29/18

    Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

    Memory system and memory controller
    20.
    发明授权
    Memory system and memory controller 有权

    公开(公告)号：US11545223B2

    公开(公告)日：2023-01-03

    申请号：US17117937

    申请日：2020-12-10

    Applicant: Kioxia Corporation

    Inventor： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H01L27/115

    Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

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