公开(公告)号：US20210375372A1

公开(公告)日：2021-12-02

申请号：US17117937

申请日：2020-12-10

Applicant: Kioxia Corporation

Inventor： Kenji SAKURADA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A memory system in an embodiment includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US20210090643A1

公开(公告)日：2021-03-25

申请号：US17018684

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20240127893A1

公开(公告)日：2024-04-18

申请号：US18222640

申请日：2023-07-17

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/3418 ,  G11C16/3486

Abstract: According to one embodiment, a memory system includes 1st-5th sub-memory regions and a controller, the controller being configured to: calculate a 1st voltage of the 1st sub-memory region in 1st processing; calculate a 2nd voltage of the 4th sub-memory region in 2nd processing; before the 1st processing, use a 3rd voltage when reading the 1st and 2nd sub-memory regions, and the 4th and the 5th sub-memory regions, and use a 4th voltage of the 3rd sub-memory region when reading the 3rd sub-memory region; use the 1st voltage when reading the 1st sub-memory region, use a 5th voltage calculated by using the 1st voltage when reading the 2nd, the 4th, and the 5th sub-memory regions, use a 6th voltage calculated by using the 2nd voltage when reading the 2nd and the 5th sub-memory regions.

公开(公告)号：US20240095112A1

公开(公告)日：2024-03-21

申请号：US18450239

申请日：2023-08-15

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA

IPC: G06F11/07 ,  G06F12/02

CPC classification number: G06F11/073 ,  G06F12/0246

Abstract: According to an embodiment, a controller acquires a first temperature detection value and executes an acquisition operation on a first storage area. The controller converts a first voltage value into a second voltage value representing the read voltage in a temperature set value based on the first temperature detection value and records the second voltage value. The acquisition operation is an operation of determining, by using the read voltages, whether memory cells are ON or OFF and acquiring the first voltage value representing the read voltage for suppressing error bits. After that, the controller acquires a second temperature detection value and converts the second voltage value into a third voltage value representing the read voltage in the second temperature detection value. The controller reads data from the memory cells by using, as the read voltage, a voltage indicated by the third voltage value.

公开(公告)号：US20230395144A1

公开(公告)日：2023-12-07

申请号：US18451182

申请日：2023-08-17

Applicant: KIOXIA CORPORATION

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G06F12/0246

Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20230305753A1

公开(公告)日：2023-09-28

申请号：US18309038

申请日：2023-04-28

Applicant: KIOXIA CORPORATION

Inventor： Yuta AIBA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G06F3/06 ,  G11C19/08

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0679 ,  G11C19/0841

Abstract: According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

公开(公告)号：US20230088099A1

公开(公告)日：2023-03-23

申请号：US18053271

申请日：2022-11-07

Applicant: Kioxia Corporation

Inventor： Kenji SAKURADA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US20220066688A1

公开(公告)日：2022-03-03

申请号：US17201092

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA ,  Hideki YAMADA

IPC: G06F3/06

Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

公开(公告)号：US20210217476A1

公开(公告)日：2021-07-15

申请号：US17018034

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Naomi TAKEDA

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first and second memory cell each configured to store data and coupled in parallel to a bit line, a first word line coupled to the first memory cell, and a second word line coupled to the second memory cell and differing from the first word line. The first and second memory cell face each other between the first word line and the second word line. The memory controller is configured to read first data from the first memory cell, read second data from the second memory cell, and decode data stored in the first memory cell based on the first data and the second data.

公开(公告)号：US20240363186A1

公开(公告)日：2024-10-31

申请号：US18764906

申请日：2024-07-05

Applicant: KIOXIA CORPORATION

Inventor： Naomi TAKEDA ,  Masanobu SHIRAKAWA

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.